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authorJakob Stoklund Olesen <stoklund@2pi.dk>2012-08-08 23:44:07 +0000
committerJakob Stoklund Olesen <stoklund@2pi.dk>2012-08-08 23:44:07 +0000
commit990ab1d2135c5a9052c67ab925edf3c59d6292ca (patch)
treeb3585cd5d4cbb57cd9ca1e36e60fb1050f585e76
parent978c1280a5ae3262fd872dacfab07610b250a235 (diff)
downloadbcm5719-llvm-990ab1d2135c5a9052c67ab925edf3c59d6292ca.tar.gz
bcm5719-llvm-990ab1d2135c5a9052c67ab925edf3c59d6292ca.zip
Move getNextOperandForReg() into MachineRegisterInfo.
MRI provides iterators for traversing the use-def chains. They should not be accessible from anywhere else. llvm-svn: 161543
-rw-r--r--llvm/include/llvm/CodeGen/MachineOperand.h12
-rw-r--r--llvm/include/llvm/CodeGen/MachineRegisterInfo.h13
2 files changed, 14 insertions, 11 deletions
diff --git a/llvm/include/llvm/CodeGen/MachineOperand.h b/llvm/include/llvm/CodeGen/MachineOperand.h
index c08b22d105e..d3cf090f951 100644
--- a/llvm/include/llvm/CodeGen/MachineOperand.h
+++ b/llvm/include/llvm/CodeGen/MachineOperand.h
@@ -138,6 +138,9 @@ private:
/// This is valid for all operand types, when the operand is in an instr.
MachineInstr *ParentMI;
+ // MRI accesses Contents.Reg directly.
+ friend class MachineRegisterInfo;
+
/// Contents union - This contains the payload for the various operand types.
union {
MachineBasicBlock *MBB; // For MO_MachineBasicBlock.
@@ -305,15 +308,6 @@ public:
return !isUndef() && !isInternalRead() && (isUse() || getSubReg());
}
- /// getNextOperandForReg - Return the next MachineOperand in the linked list
- /// of operands that use or define the same register.
- /// Don't call this function directly, see the def-use iterators in
- /// MachineRegisterInfo instead.
- MachineOperand *getNextOperandForReg() const {
- assert(isReg() && "This is not a register operand!");
- return Contents.Reg.Next;
- }
-
//===--------------------------------------------------------------------===//
// Mutators for Register Operands
//===--------------------------------------------------------------------===//
diff --git a/llvm/include/llvm/CodeGen/MachineRegisterInfo.h b/llvm/include/llvm/CodeGen/MachineRegisterInfo.h
index 061d60a23ef..aad79f624b5 100644
--- a/llvm/include/llvm/CodeGen/MachineRegisterInfo.h
+++ b/llvm/include/llvm/CodeGen/MachineRegisterInfo.h
@@ -57,6 +57,12 @@ class MachineRegisterInfo {
/// physical registers.
MachineOperand **PhysRegUseDefLists;
+ /// Get the next element in the use-def chain.
+ static MachineOperand *getNextOperandForReg(const MachineOperand *MO) {
+ assert(MO && MO->isReg() && "This is not a register operand!");
+ return MO->Contents.Reg.Next;
+ }
+
/// UsedPhysRegs - This is a bit vector that is computed and set by the
/// register allocator, and must be kept up to date by passes that run after
/// register allocation (though most don't modify this). This is used
@@ -135,6 +141,9 @@ public:
template<bool Uses, bool Defs, bool SkipDebug>
class defusechain_iterator;
+ // Make it a friend so it can access getNextOperandForReg().
+ template<bool, bool, bool> friend class defusechain_iterator;
+
/// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified
/// register.
typedef defusechain_iterator<true,true,false> reg_iterator;
@@ -500,13 +509,13 @@ public:
// Iterator traversal: forward iteration only
defusechain_iterator &operator++() { // Preincrement
assert(Op && "Cannot increment end iterator!");
- Op = Op->getNextOperandForReg();
+ Op = getNextOperandForReg(Op);
// If this is an operand we don't care about, skip it.
while (Op && ((!ReturnUses && Op->isUse()) ||
(!ReturnDefs && Op->isDef()) ||
(SkipDebug && Op->isDebug())))
- Op = Op->getNextOperandForReg();
+ Op = getNextOperandForReg(Op);
return *this;
}
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