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| author | Igor Breger <igor.breger@intel.com> | 2016-06-08 07:48:23 +0000 |
|---|---|---|
| committer | Igor Breger <igor.breger@intel.com> | 2016-06-08 07:48:23 +0000 |
| commit | 982e4003a62b00ee16712a99e8fb414e265a1660 (patch) | |
| tree | e691487c0ea49731b1b183408cc23a7dd4d4bb78 | |
| parent | 50e94a3b34128ae1e4bbb636dce62d9bc8cf67ff (diff) | |
| download | bcm5719-llvm-982e4003a62b00ee16712a99e8fb414e265a1660.tar.gz bcm5719-llvm-982e4003a62b00ee16712a99e8fb414e265a1660.zip | |
[AVX512] Fix cvtusi2sd instruction Opcode, it should be 0x7B instead of 0x2A.
llvm-svn: 272122
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrAVX512.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index 47891910d64..0ab57db9403 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -5097,7 +5097,7 @@ let isCodeGenOnly = 1 , Predicates = [HasAVX512] in { int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}", SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W; - defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X, + defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x7B, GR32, VR128X, int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}", SSE_CVT_Scalar, 0>, XD, EVEX_4V; } // isCodeGenOnly = 1, Predicates = [HasAVX512] |
