Move target independent td files from lib/Target/ to include/llvm/Target so they can be distributed along with the header files.

llvm-svn: 59953

15 files changed, 17 insertions, 16 deletions

diff --git a/llvm/Makefile.rules b/llvm/Makefile.rules
index 849c70bc04c..82a108e2438 100644
--- a/llvm/Makefile.rules
+++ b/llvm/Makefile.rules
@@ -1259,9 +1259,10 @@ $(ObjDir)/%.bc: %.ll $(ObjDir)/.dir $(LLVMAS)
 ifdef TARGET
 
 TDFiles := $(strip $(wildcard $(PROJ_SRC_DIR)/*.td) \
-           $(LLVM_SRC_ROOT)/lib/Target/Target.td \
-           $(LLVM_SRC_ROOT)/lib/Target/TargetCallingConv.td \
-           $(LLVM_SRC_ROOT)/lib/Target/TargetSelectionDAG.td \
+           $(LLVM_SRC_ROOT)/include/llvm/Target/Target.td \
+           $(LLVM_SRC_ROOT)/include/llvm/Target/TargetCallingConv.td \
+           $(LLVM_SRC_ROOT)/include/llvm/Target/TargetSchedule.td \
+           $(LLVM_SRC_ROOT)/include/llvm/Target/TargetSelectionDAG.td \
            $(LLVM_SRC_ROOT)/include/llvm/CodeGen/ValueTypes.td) \
            $(wildcard $(LLVM_SRC_ROOT)/include/llvm/Intrinsics*.td)
 INCFiles := $(filter %.inc,$(BUILT_SOURCES))
diff --git a/llvm/lib/Target/Target.td b/llvm/include/llvm/Target/Target.td
index e07529d708e..91e44f23a52 100644
--- a/llvm/lib/Target/Target.td
+++ b/llvm/include/llvm/Target/Target.td
@@ -147,7 +147,7 @@ class DwarfRegNum<list<int> Numbers> {
 //===----------------------------------------------------------------------===//
 // Pull in the common support for scheduling
 //
-include "TargetSchedule.td"
+include "llvm/Target/TargetSchedule.td"
 
 class Predicate; // Forward def
 
@@ -491,9 +491,9 @@ class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
 //===----------------------------------------------------------------------===//
 // Pull in the common support for calling conventions.
 //
-include "TargetCallingConv.td"
+include "llvm/Target/TargetCallingConv.td"
 
 //===----------------------------------------------------------------------===//
 // Pull in the common support for DAG isel generation.
 //
-include "TargetSelectionDAG.td"
+include "llvm/Target/TargetSelectionDAG.td"
diff --git a/llvm/lib/Target/TargetCallingConv.td b/llvm/include/llvm/Target/TargetCallingConv.td
index 908e16ed5e7..908e16ed5e7 100644
--- a/llvm/lib/Target/TargetCallingConv.td
+++ b/llvm/include/llvm/Target/TargetCallingConv.td
diff --git a/llvm/lib/Target/TargetSchedule.td b/llvm/include/llvm/Target/TargetSchedule.td
index 38461c5a380..38461c5a380 100644
--- a/llvm/lib/Target/TargetSchedule.td
+++ b/llvm/include/llvm/Target/TargetSchedule.td
diff --git a/llvm/lib/Target/TargetSelectionDAG.td b/llvm/include/llvm/Target/TargetSelectionDAG.td
index c936f7af4c6..c936f7af4c6 100644
--- a/llvm/lib/Target/TargetSelectionDAG.td
+++ b/llvm/include/llvm/Target/TargetSelectionDAG.td
diff --git a/llvm/lib/Target/ARM/ARM.td b/llvm/lib/Target/ARM/ARM.td
index 19e25d4f9d7..aca868fd763 100644
--- a/llvm/lib/Target/ARM/ARM.td
+++ b/llvm/lib/Target/ARM/ARM.td
@@ -14,7 +14,7 @@
 // Target-independent interfaces which we are implementing
 //===----------------------------------------------------------------------===//
 
-include "../Target.td"
+include "llvm/Target/Target.td"
 
 //===----------------------------------------------------------------------===//
 // ARM Subtarget features.
diff --git a/llvm/lib/Target/Alpha/Alpha.td b/llvm/lib/Target/Alpha/Alpha.td
index 65a760bdbe0..e3748c6a09f 100644
--- a/llvm/lib/Target/Alpha/Alpha.td
+++ b/llvm/lib/Target/Alpha/Alpha.td
@@ -12,7 +12,7 @@
 
 // Get the target-independent interfaces which we are implementing...
 //
-include "../Target.td"
+include "llvm/Target/Target.td"
 
 //Alpha is little endian
 
diff --git a/llvm/lib/Target/CellSPU/SPU.td b/llvm/lib/Target/CellSPU/SPU.td
index 15809f208b2..a5db1d9d2b5 100644
--- a/llvm/lib/Target/CellSPU/SPU.td
+++ b/llvm/lib/Target/CellSPU/SPU.td
@@ -13,7 +13,7 @@
 
 // Get the target-independent interfaces which we are implementing.
 //
-include "../Target.td"
+include "llvm/Target/Target.td"
 
 //===----------------------------------------------------------------------===//
 // Register File Description
diff --git a/llvm/lib/Target/IA64/IA64.td b/llvm/lib/Target/IA64/IA64.td
index 0cef72e5c45..c469281ab16 100644
--- a/llvm/lib/Target/IA64/IA64.td
+++ b/llvm/lib/Target/IA64/IA64.td
@@ -14,7 +14,7 @@
 
 // Get the target-independent interfaces which we are implementing...
 //
-include "../Target.td"
+include "llvm/Target/Target.td"
 
 //===----------------------------------------------------------------------===//
 // Register File Description
diff --git a/llvm/lib/Target/Mips/Mips.td b/llvm/lib/Target/Mips/Mips.td
index 79c18902465..79ae5d2425f 100644
--- a/llvm/lib/Target/Mips/Mips.td
+++ b/llvm/lib/Target/Mips/Mips.td
@@ -13,7 +13,7 @@
 // Target-independent interfaces
 //===----------------------------------------------------------------------===//
 
-include "../Target.td"
+include "llvm/Target/Target.td"
 
 //===----------------------------------------------------------------------===//
 // Register File, Calling Conv, Instruction Descriptions
diff --git a/llvm/lib/Target/PIC16/PIC16.td b/llvm/lib/Target/PIC16/PIC16.td
index d37075b1cb1..b2b9b1cd171 100644
--- a/llvm/lib/Target/PIC16/PIC16.td
+++ b/llvm/lib/Target/PIC16/PIC16.td
@@ -13,7 +13,7 @@
 // Target-independent interfaces
 //===----------------------------------------------------------------------===//
 
-include "../Target.td"
+include "llvm/Target/Target.td"
 
 include "PIC16RegisterInfo.td"
 include "PIC16InstrInfo.td"
diff --git a/llvm/lib/Target/PowerPC/PPC.td b/llvm/lib/Target/PowerPC/PPC.td
index cc0c8c8fa63..08f5bb43087 100644
--- a/llvm/lib/Target/PowerPC/PPC.td
+++ b/llvm/lib/Target/PowerPC/PPC.td
@@ -13,7 +13,7 @@
 
 // Get the target-independent interfaces which we are implementing.
 //
-include "../Target.td"
+include "llvm/Target/Target.td"
 
 //===----------------------------------------------------------------------===//
 // PowerPC Subtarget features.
diff --git a/llvm/lib/Target/Sparc/Sparc.td b/llvm/lib/Target/Sparc/Sparc.td
index b90fcdedaeb..53ea8f4a35f 100644
--- a/llvm/lib/Target/Sparc/Sparc.td
+++ b/llvm/lib/Target/Sparc/Sparc.td
@@ -14,7 +14,7 @@
 // Target-independent interfaces which we are implementing
 //===----------------------------------------------------------------------===//
 
-include "../Target.td"
+include "llvm/Target/Target.td"
 
 //===----------------------------------------------------------------------===//
 // SPARC Subtarget features.
diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td
index f70c17592ce..6d08b36be44 100644
--- a/llvm/lib/Target/X86/X86.td
+++ b/llvm/lib/Target/X86/X86.td
@@ -14,7 +14,7 @@
 
 // Get the target-independent interfaces which we are implementing...
 //
-include "../Target.td"
+include "llvm/Target/Target.td"
 
 //===----------------------------------------------------------------------===//
 // X86 Subtarget features.
diff --git a/llvm/lib/Target/XCore/XCore.td b/llvm/lib/Target/XCore/XCore.td
index 39c4226b616..7a2dcdbf9fe 100644
--- a/llvm/lib/Target/XCore/XCore.td
+++ b/llvm/lib/Target/XCore/XCore.td
@@ -14,7 +14,7 @@
 // Target-independent interfaces which we are implementing
 //===----------------------------------------------------------------------===//
 
-include "../Target.td"
+include "llvm/Target/Target.td"
 
 //===----------------------------------------------------------------------===//
 // Descriptions