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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2019-06-25 16:00:16 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2019-06-25 16:00:16 +0000 |
| commit | 9762b26032c8b926fc2a77b30c93c2aacc52a46e (patch) | |
| tree | 061add7fb32cd518ce979c33109dc11d2c52c45b | |
| parent | 635eb80662d9a2df12d45748df064d000bf96530 (diff) | |
| download | bcm5719-llvm-9762b26032c8b926fc2a77b30c93c2aacc52a46e.tar.gz bcm5719-llvm-9762b26032c8b926fc2a77b30c93c2aacc52a46e.zip | |
[DAGCombine] combineRepeatedFPDivisors - recognize -1.0 / X as a reciprocal
Fixes issue identified by @nemanjai (Nemanja Ivanovic) in D62963 / rL363040 - infinite loop due to GetNegatedExpression fighting combineRepeatedFPDivisors resulting in fneg(fdiv(x,splat)) -> fneg(fmul(x,1.0/splat)) -> fmul(x,-1.0/splat) -> fmul(x,(-1.0 * 1.0)/splat) ......
llvm-svn: 364326
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/combine-fneg.ll | 32 |
2 files changed, 34 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 1e160c4097f..06123487f50 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -12362,10 +12362,10 @@ SDValue DAGCombiner::combineRepeatedFPDivisors(SDNode *N) { if (!UnsafeMath && !Flags.hasAllowReciprocal()) return SDValue(); - // Skip if current node is a reciprocal. + // Skip if current node is a reciprocal/fneg-reciprocal. SDValue N0 = N->getOperand(0); ConstantFPSDNode *N0CFP = isConstOrConstSplatFP(N0, /* AllowUndefs */ true); - if (N0CFP && N0CFP->isExactlyValue(1.0)) + if (N0CFP && (N0CFP->isExactlyValue(1.0) || N0CFP->isExactlyValue(-1.0))) return SDValue(); // Exit early if the target does not want this transform or if there can't diff --git a/llvm/test/CodeGen/PowerPC/combine-fneg.ll b/llvm/test/CodeGen/PowerPC/combine-fneg.ll new file mode 100644 index 00000000000..864f723575f --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/combine-fneg.ll @@ -0,0 +1,32 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=powerpc64le-unknown-unknown | FileCheck %s + +; Infinite loop identified in D62963. +define <4 x double> @fneg_fdiv_splat(double %a0, <4 x double> %a1) { +; CHECK-LABEL: fneg_fdiv_splat: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: # kill: def $f1 killed $f1 def $vsl1 +; CHECK-NEXT: xxspltd 0, 1, 0 +; CHECK-NEXT: addis 3, 2, .LCPI0_0@toc@ha +; CHECK-NEXT: addi 3, 3, .LCPI0_0@toc@l +; CHECK-NEXT: lxvd2x 1, 0, 3 +; CHECK-NEXT: addis 3, 2, .LCPI0_1@toc@ha +; CHECK-NEXT: xvredp 2, 0 +; CHECK-NEXT: addi 3, 3, .LCPI0_1@toc@l +; CHECK-NEXT: xxswapd 1, 1 +; CHECK-NEXT: xvnmsubadp 1, 2, 0 +; CHECK-NEXT: xvmaddadp 2, 2, 1 +; CHECK-NEXT: lxvd2x 1, 0, 3 +; CHECK-NEXT: xxswapd 1, 1 +; CHECK-NEXT: xvmaddadp 1, 0, 2 +; CHECK-NEXT: xvmsubadp 2, 2, 1 +; CHECK-NEXT: xvmuldp 34, 34, 2 +; CHECK-NEXT: xvmuldp 35, 35, 2 +; CHECK-NEXT: blr +entry: + %splat.splatinsert = insertelement <4 x double> undef, double %a0, i32 0 + %splat.splat = shufflevector <4 x double> %splat.splatinsert, <4 x double> undef, <4 x i32> zeroinitializer + %div = fdiv fast <4 x double> %a1, %splat.splat + %sub = fsub fast <4 x double> <double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00>, %div + ret <4 x double> %sub +} |
