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| author | Sanjay Patel <spatel@rotateright.com> | 2016-09-30 18:10:14 +0000 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2016-09-30 18:10:14 +0000 |
| commit | 9685b3eb579357fd639ce74a26fc75dec2084be8 (patch) | |
| tree | 4fb0d45781c530d6b58169232fdef6144ec39e5a | |
| parent | e9e6891b2d801de637496059be696d89f522d72d (diff) | |
| download | bcm5719-llvm-9685b3eb579357fd639ce74a26fc75dec2084be8.tar.gz bcm5719-llvm-9685b3eb579357fd639ce74a26fc75dec2084be8.zip | |
[InstCombine] add tests for select X, (ext X), C
llvm-svn: 282891
| -rw-r--r-- | llvm/test/Transforms/InstCombine/select-bitext.ll | 91 |
1 files changed, 91 insertions, 0 deletions
diff --git a/llvm/test/Transforms/InstCombine/select-bitext.ll b/llvm/test/Transforms/InstCombine/select-bitext.ll index fc379d28a73..34e260a286d 100644 --- a/llvm/test/Transforms/InstCombine/select-bitext.ll +++ b/llvm/test/Transforms/InstCombine/select-bitext.ll @@ -198,3 +198,94 @@ define <2 x i32> @scalar_select_of_vectors_zext(<2 x i1> %cca, i1 %ccb) { %r = select i1 %ccb, <2 x i32> %ccax, <2 x i32> <i32 0, i32 0> ret <2 x i32> %r } + +define i32 @sext_true_val_must_be_all_ones(i1 %x) { +; CHECK-LABEL: @sext_true_val_must_be_all_ones( +; CHECK-NEXT: [[EXT:%.*]] = sext i1 %x to i32 +; CHECK-NEXT: [[SEL:%.*]] = select i1 %x, i32 [[EXT]], i32 42, !prof !0 +; CHECK-NEXT: ret i32 [[SEL]] +; + %ext = sext i1 %x to i32 + %sel = select i1 %x, i32 %ext, i32 42, !prof !0 + ret i32 %sel +} + +define <2 x i32> @sext_true_val_must_be_all_ones_vec(<2 x i1> %x) { +; CHECK-LABEL: @sext_true_val_must_be_all_ones_vec( +; CHECK-NEXT: [[EXT:%.*]] = sext <2 x i1> %x to <2 x i32> +; CHECK-NEXT: [[SEL:%.*]] = select <2 x i1> %x, <2 x i32> [[EXT]], <2 x i32> <i32 42, i32 12>, !prof !0 +; CHECK-NEXT: ret <2 x i32> [[SEL]] +; + %ext = sext <2 x i1> %x to <2 x i32> + %sel = select <2 x i1> %x, <2 x i32> %ext, <2 x i32> <i32 42, i32 12>, !prof !0 + ret <2 x i32> %sel +} + +define i32 @zext_true_val_must_be_one(i1 %x) { +; CHECK-LABEL: @zext_true_val_must_be_one( +; CHECK-NEXT: [[EXT:%.*]] = zext i1 %x to i32 +; CHECK-NEXT: [[SEL:%.*]] = select i1 %x, i32 [[EXT]], i32 42, !prof !0 +; CHECK-NEXT: ret i32 [[SEL]] +; + %ext = zext i1 %x to i32 + %sel = select i1 %x, i32 %ext, i32 42, !prof !0 + ret i32 %sel +} + +define <2 x i32> @zext_true_val_must_be_one_vec(<2 x i1> %x) { +; CHECK-LABEL: @zext_true_val_must_be_one_vec( +; CHECK-NEXT: [[EXT:%.*]] = zext <2 x i1> %x to <2 x i32> +; CHECK-NEXT: [[SEL:%.*]] = select <2 x i1> %x, <2 x i32> [[EXT]], <2 x i32> <i32 42, i32 12>, !prof !0 +; CHECK-NEXT: ret <2 x i32> [[SEL]] +; + %ext = zext <2 x i1> %x to <2 x i32> + %sel = select <2 x i1> %x, <2 x i32> %ext, <2 x i32> <i32 42, i32 12>, !prof !0 + ret <2 x i32> %sel +} + +define i32 @sext_false_val_must_be_zero(i1 %x) { +; CHECK-LABEL: @sext_false_val_must_be_zero( +; CHECK-NEXT: [[EXT:%.*]] = sext i1 %x to i32 +; CHECK-NEXT: [[SEL:%.*]] = select i1 %x, i32 42, i32 [[EXT]], !prof !0 +; CHECK-NEXT: ret i32 [[SEL]] +; + %ext = sext i1 %x to i32 + %sel = select i1 %x, i32 42, i32 %ext, !prof !0 + ret i32 %sel +} + +define <2 x i32> @sext_false_val_must_be_zero_vec(<2 x i1> %x) { +; CHECK-LABEL: @sext_false_val_must_be_zero_vec( +; CHECK-NEXT: [[EXT:%.*]] = sext <2 x i1> %x to <2 x i32> +; CHECK-NEXT: [[SEL:%.*]] = select <2 x i1> %x, <2 x i32> <i32 42, i32 12>, <2 x i32> [[EXT]], !prof !0 +; CHECK-NEXT: ret <2 x i32> [[SEL]] +; + %ext = sext <2 x i1> %x to <2 x i32> + %sel = select <2 x i1> %x, <2 x i32> <i32 42, i32 12>, <2 x i32> %ext, !prof !0 + ret <2 x i32> %sel +} + +define i32 @zext_false_val_must_be_zero(i1 %x) { +; CHECK-LABEL: @zext_false_val_must_be_zero( +; CHECK-NEXT: [[EXT:%.*]] = zext i1 %x to i32 +; CHECK-NEXT: [[SEL:%.*]] = select i1 %x, i32 42, i32 [[EXT]], !prof !0 +; CHECK-NEXT: ret i32 [[SEL]] +; + %ext = zext i1 %x to i32 + %sel = select i1 %x, i32 42, i32 %ext, !prof !0 + ret i32 %sel +} + +define <2 x i32> @zext_false_val_must_be_zero_vec(<2 x i1> %x) { +; CHECK-LABEL: @zext_false_val_must_be_zero_vec( +; CHECK-NEXT: [[EXT:%.*]] = zext <2 x i1> %x to <2 x i32> +; CHECK-NEXT: [[SEL:%.*]] = select <2 x i1> %x, <2 x i32> <i32 42, i32 12>, <2 x i32> [[EXT]], !prof !0 +; CHECK-NEXT: ret <2 x i32> [[SEL]] +; + %ext = zext <2 x i1> %x to <2 x i32> + %sel = select <2 x i1> %x, <2 x i32> <i32 42, i32 12>, <2 x i32> %ext, !prof !0 + ret <2 x i32> %sel +} + +!0 = !{!"branch_weights", i32 3, i32 5} + |
