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authorMatt Arsenault <Matthew.Arsenault@amd.com>2019-05-16 04:08:55 +0000
committerMatt Arsenault <Matthew.Arsenault@amd.com>2019-05-16 04:08:55 +0000
commit940a9ff0f3bf38d36ce050ef15a4abb1bce1beea (patch)
treefdfe4b94aea0e999a8ed3991eaff2ac6dc7888af
parent012ecbbbbadf99eb035b599c431bf2938b889f5b (diff)
downloadbcm5719-llvm-940a9ff0f3bf38d36ce050ef15a4abb1bce1beea.tar.gz
bcm5719-llvm-940a9ff0f3bf38d36ce050ef15a4abb1bce1beea.zip
GlobalISel: Add some FP instructions to MachineIRBuilder
This makes FP legalization code more convenient. llvm-svn: 360852
-rw-r--r--llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h28
-rw-r--r--llvm/unittests/CodeGen/GlobalISel/MachineIRBuilderTest.cpp28
2 files changed, 56 insertions, 0 deletions
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
index 9768960e171..ee1e2daca22 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
@@ -1239,6 +1239,34 @@ public:
return buildInstr(TargetOpcode::G_OR, {Dst}, {Src0, Src1});
}
+ /// Build and insert \p Res = G_FADD \p Op0, \p Op1
+ MachineInstrBuilder buildFAdd(const DstOp &Dst, const SrcOp &Src0,
+ const SrcOp &Src1) {
+ return buildInstr(TargetOpcode::G_FADD, {Dst}, {Src0, Src1});
+ }
+
+ /// Build and insert \p Res = G_FSUB \p Op0, \p Op1
+ MachineInstrBuilder buildFSub(const DstOp &Dst, const SrcOp &Src0,
+ const SrcOp &Src1) {
+ return buildInstr(TargetOpcode::G_FSUB, {Dst}, {Src0, Src1});
+ }
+
+ /// Build and insert \p Res = G_FNEG \p Op0
+ MachineInstrBuilder buildFNeg(const DstOp &Dst, const SrcOp &Src0) {
+ return buildInstr(TargetOpcode::G_FNEG, {Dst}, {Src0});
+ }
+
+ /// Build and insert \p Res = G_FABS \p Op0
+ MachineInstrBuilder buildFAbs(const DstOp &Dst, const SrcOp &Src0) {
+ return buildInstr(TargetOpcode::G_FABS, {Dst}, {Src0});
+ }
+
+ /// Build and insert \p Res = G_FCOPYSIGN \p Op0, \p Op1
+ MachineInstrBuilder buildFCopysign(const DstOp &Dst, const SrcOp &Src0,
+ const SrcOp &Src1) {
+ return buildInstr(TargetOpcode::G_FCOPYSIGN, {Dst}, {Src0, Src1});
+ }
+
virtual MachineInstrBuilder buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps,
ArrayRef<SrcOp> SrcOps,
Optional<unsigned> Flags = None);
diff --git a/llvm/unittests/CodeGen/GlobalISel/MachineIRBuilderTest.cpp b/llvm/unittests/CodeGen/GlobalISel/MachineIRBuilderTest.cpp
index 7817f721bda..e53dc80005d 100644
--- a/llvm/unittests/CodeGen/GlobalISel/MachineIRBuilderTest.cpp
+++ b/llvm/unittests/CodeGen/GlobalISel/MachineIRBuilderTest.cpp
@@ -110,3 +110,31 @@ TEST_F(GISelMITest, BuildUnmerge) {
EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
}
+
+TEST_F(GISelMITest, TestBuildFPInsts) {
+ if (!TM)
+ return;
+
+ SmallVector<unsigned, 4> Copies;
+ collectCopies(Copies, MF);
+
+ LLT S64 = LLT::scalar(64);
+
+ B.buildFAdd(S64, Copies[0], Copies[1]);
+ B.buildFSub(S64, Copies[0], Copies[1]);
+ B.buildFNeg(S64, Copies[0]);
+ B.buildFAbs(S64, Copies[0]);
+ B.buildFCopysign(S64, Copies[0], Copies[1]);
+
+ auto CheckStr = R"(
+ ; CHECK: [[COPY0:%[0-9]+]]:_(s64) = COPY $x0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
+ ; CHECK: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[COPY0]]:_, [[COPY1]]:_
+ ; CHECK: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[COPY0]]:_, [[COPY1]]:_
+ ; CHECK: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[COPY0]]:_
+ ; CHECK: [[FABS:%[0-9]+]]:_(s64) = G_FABS [[COPY0]]:_
+ ; CHECK: [[FCOPYSIGN:%[0-9]+]]:_(s64) = G_FCOPYSIGN [[COPY0]]:_, [[COPY1]]:_
+ )";
+
+ EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
+}
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