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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-01-17 14:17:34 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-01-17 14:17:34 +0000 |
| commit | 9342557ea70c08f50391fc1e8d9df82db21ad2ae (patch) | |
| tree | b18f51ca2e35df870d7713fcd24527bc41e94519 | |
| parent | a9b3aee516211c4c92e2d5f8e7c7600d68cc5021 (diff) | |
| download | bcm5719-llvm-9342557ea70c08f50391fc1e8d9df82db21ad2ae.tar.gz bcm5719-llvm-9342557ea70c08f50391fc1e8d9df82db21ad2ae.zip | |
[mips][sched] Split IIHiLo into II_MFHI_MFLO and II_MTHI_MTLO
No functional change since the InstrItinData's have been duplicated.
llvm-svn: 199493
| -rw-r--r-- | llvm/lib/Target/Mips/MipsInstrInfo.td | 11 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MipsSchedule.td | 6 |
2 files changed, 10 insertions, 7 deletions
diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td index 4e56132e61f..227c788cc6e 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsInstrInfo.td @@ -727,21 +727,22 @@ class Div<string opstr, InstrItinClass itin, RegisterOperand RO, // Move from Hi/Lo class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode> : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo), - [(set DstRC:$rd, (OpNode SrcRC:$hilo))], IIHiLo>; + [(set DstRC:$rd, (OpNode SrcRC:$hilo))], II_MFHI_MFLO>; class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>: - InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], IIHiLo, FrmR, - opstr> { + InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], II_MFHI_MFLO, + FrmR, opstr> { let Uses = [UseReg]; let neverHasSideEffects = 1; } class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC> : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi), - [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))], IIHiLo>; + [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))], + II_MTHI_MTLO>; class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>: - InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], IIHiLo, + InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], II_MTHI_MTLO, FrmR, opstr> { let Defs = DefRegs; let neverHasSideEffects = 1; diff --git a/llvm/lib/Target/Mips/MipsSchedule.td b/llvm/lib/Target/Mips/MipsSchedule.td index 20cd8fd0b0c..953fff0a515 100644 --- a/llvm/lib/Target/Mips/MipsSchedule.td +++ b/llvm/lib/Target/Mips/MipsSchedule.td @@ -20,7 +20,6 @@ def IIAlu : InstrItinClass; def IILoad : InstrItinClass; def IIStore : InstrItinClass; def IIBranch : InstrItinClass; -def IIHiLo : InstrItinClass; def IIImul : InstrItinClass; def IIImult : InstrItinClass; def IIIdiv : InstrItinClass; @@ -64,6 +63,8 @@ def II_DSRL32 : InstrItinClass; def II_DSRLV : InstrItinClass; def II_DSUBU : InstrItinClass; def II_LUI : InstrItinClass; +def II_MFHI_MFLO : InstrItinClass; // mfhi and mflo +def II_MTHI_MTLO : InstrItinClass; // mthi and mtlo def II_MOVF : InstrItinClass; def II_MOVN : InstrItinClass; def II_MOVT : InstrItinClass; @@ -132,7 +133,8 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [ InstrItinData<IILoad , [InstrStage<3, [ALU]>]>, InstrItinData<IIStore , [InstrStage<1, [ALU]>]>, InstrItinData<IIBranch , [InstrStage<1, [ALU]>]>, - InstrItinData<IIHiLo , [InstrStage<1, [IMULDIV]>]>, + InstrItinData<II_MFHI_MFLO , [InstrStage<1, [IMULDIV]>]>, + InstrItinData<II_MTHI_MTLO , [InstrStage<1, [IMULDIV]>]>, InstrItinData<IIImul , [InstrStage<17, [IMULDIV]>]>, InstrItinData<IIImult , [InstrStage<17, [IMULDIV]>]>, InstrItinData<IIIdiv , [InstrStage<38, [IMULDIV]>]>, |
