GlobalISel: IRTranslate llvm.fmuladd.* intrinsic

Reviewers: qcolombet, ab, dsanders, aditya_nandakumar, bogner

Reviewed By: qcolombet

Subscribers: rovka, kristof.beyls, javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D43090

llvm-svn: 324971

2 files changed, 53 insertions, 0 deletions

diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index c4fae823c1e..bafca2499e4 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -753,6 +753,25 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
         .addUse(getOrCreateVReg(*CI.getArgOperand(1)))
         .addUse(getOrCreateVReg(*CI.getArgOperand(2)));
     return true;
+  case Intrinsic::fmuladd: {
+    const TargetMachine &TM = MF->getTarget();
+    const TargetLowering &TLI = *MF->getSubtarget().getTargetLowering();
+    unsigned Dst = getOrCreateVReg(CI);
+    unsigned Op0 = getOrCreateVReg(*CI.getArgOperand(0));
+    unsigned Op1 = getOrCreateVReg(*CI.getArgOperand(1));
+    unsigned Op2 = getOrCreateVReg(*CI.getArgOperand(2));
+    if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
+        TLI.isFMAFasterThanFMulAndFAdd(TLI.getValueType(*DL, CI.getType()))) {
+      // TODO: Revisit this to see if we should move this part of the
+      // lowering to the combiner.
+      MIRBuilder.buildInstr(TargetOpcode::G_FMA, Dst, Op0, Op1, Op2);
+    } else {
+      LLT Ty = getLLTForType(*CI.getType(), *DL);
+      auto FMul = MIRBuilder.buildInstr(TargetOpcode::G_FMUL, Ty, Op0, Op1);
+      MIRBuilder.buildInstr(TargetOpcode::G_FADD, Dst, FMul, Op2);
+    }
+    return true;
+  }
   case Intrinsic::memcpy:
   case Intrinsic::memmove:
   case Intrinsic::memset:
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-fmuladd.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-fmuladd.ll
new file mode 100644
index 00000000000..371255a11de
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-fmuladd.ll
@@ -0,0 +1,34 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+; RUN: llc -o - -verify-machineinstrs -global-isel -stop-after=irtranslator -fp-contract=fast %s | FileCheck %s --check-prefix=FPFAST
+; RUN: llc -o - -verify-machineinstrs -global-isel -stop-after=irtranslator -fp-contract=off %s | FileCheck %s --check-prefix=FPOFF
+target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+target triple = "aarch64--"
+
+define float @test_fmuladd(float %x, float %y, float %z) {
+  ; FPFAST-LABEL: name: test_fmuladd
+  ; FPFAST: bb.1 (%ir-block.0):
+  ; FPFAST:   liveins: $s0, $s1, $s2
+  ; FPFAST:   [[COPY:%[0-9]+]]:_(s32) = COPY $s0
+  ; FPFAST:   [[COPY1:%[0-9]+]]:_(s32) = COPY $s1
+  ; FPFAST:   [[COPY2:%[0-9]+]]:_(s32) = COPY $s2
+  ; FPFAST:   [[FMA:%[0-9]+]]:_(s32) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
+  ; FPFAST:   $s0 = COPY [[FMA]](s32)
+  ; FPFAST:   RET_ReallyLR implicit $s0
+  ; FPOFF-LABEL: name: test_fmuladd
+  ; FPOFF: bb.1 (%ir-block.0):
+  ; FPOFF:   liveins: $s0, $s1, $s2
+  ; FPOFF:   [[COPY:%[0-9]+]]:_(s32) = COPY $s0
+  ; FPOFF:   [[COPY1:%[0-9]+]]:_(s32) = COPY $s1
+  ; FPOFF:   [[COPY2:%[0-9]+]]:_(s32) = COPY $s2
+  ; FPOFF:   [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[COPY1]]
+  ; FPOFF:   [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[COPY2]]
+  ; FPOFF:   $s0 = COPY [[FADD]](s32)
+  ; FPOFF:   RET_ReallyLR implicit $s0
+  %res = call float @llvm.fmuladd.f32(float %x, float %y, float %z)
+  ret float %res
+}
+
+; Function Attrs: nounwind readnone speculatable
+declare float @llvm.fmuladd.f32(float, float, float) #0
+
+attributes #0 = { nounwind readnone speculatable }