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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-04-21 21:16:44 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-04-21 21:16:44 +0000 |
| commit | 920802cc50c3c424980f86a65c2736f65aaf69a0 (patch) | |
| tree | d0f89553943fbc315aaddb977ef71215348e634f | |
| parent | 2cd41eb0581496d79a6f462f3b7d0d5bc6655956 (diff) | |
| download | bcm5719-llvm-920802cc50c3c424980f86a65c2736f65aaf69a0.tar.gz bcm5719-llvm-920802cc50c3c424980f86a65c2736f65aaf69a0.zip | |
[X86] Strip unnecessary WriteCvtF2I instrw overrides from scheduler models.
llvm-svn: 330525
| -rwxr-xr-x | llvm/lib/Target/X86/X86SchedBroadwell.td | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86SchedHaswell.td | 4 |
2 files changed, 2 insertions, 6 deletions
diff --git a/llvm/lib/Target/X86/X86SchedBroadwell.td b/llvm/lib/Target/X86/X86SchedBroadwell.td index 9c681098a82..6760ad048ed 100755 --- a/llvm/lib/Target/X86/X86SchedBroadwell.td +++ b/llvm/lib/Target/X86/X86SchedBroadwell.td @@ -638,9 +638,7 @@ def: InstRW<[BWWriteResGroup27], (instregex "MMX_CVTPI2PSirr", "PEXT(32|64)rr", "SHLD(16|32|64)rri8", "SHRD(16|32|64)rri8", - "(V?)CVTDQ2PS(Y?)rr", - "(V?)CVTPS2DQ(Y?)rr", - "(V?)CVTTPS2DQ(Y?)rr")>; + "(V?)CVTDQ2PS(Y?)rr")>; def BWWriteResGroup27_16 : SchedWriteRes<[BWPort1, BWPort0156]> { let Latency = 4; diff --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td index f4da40422fd..d7adb6476cd 100644 --- a/llvm/lib/Target/X86/X86SchedHaswell.td +++ b/llvm/lib/Target/X86/X86SchedHaswell.td @@ -1484,9 +1484,7 @@ def: InstRW<[HWWriteResGroup50], (instregex "MMX_CVTPI2PSirr", "PEXT(32|64)rr", "SHLD(16|32|64)rri8", "SHRD(16|32|64)rri8", - "(V?)CVTDQ2PS(Y?)rr", - "(V?)CVTPS2DQ(Y?)rr", - "(V?)CVTTPS2DQ(Y?)rr")>; + "(V?)CVTDQ2PS(Y?)rr")>; def HWWriteResGroup50_16i : SchedWriteRes<[HWPort1, HWPort0156]> { let Latency = 4; |
