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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-12-21 00:05:18 +0530 |
|---|---|---|
| committer | Matt Arsenault <arsenm2@gmail.com> | 2019-12-24 09:53:01 -0500 |
| commit | 9035fa6b54e81ca314a5858ed05bbd2898763b67 (patch) | |
| tree | 476c00ea1d8558f7888fd440a4dcd200169bdb69 | |
| parent | 0293b5d67123786daf80528af9ef356b7bd9d2f6 (diff) | |
| download | bcm5719-llvm-9035fa6b54e81ca314a5858ed05bbd2898763b67.tar.gz bcm5719-llvm-9035fa6b54e81ca314a5858ed05bbd2898763b67.zip | |
AMDGPU/GlobalISel: Lower llvm.amdgcn.else
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 23 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-brcond.mir | 31 |
2 files changed, 48 insertions, 6 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp index cd2a02376ec..b74bec0198a 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp @@ -2295,8 +2295,10 @@ bool AMDGPULegalizerInfo::legalizeIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const { // Replace the use G_BRCOND with the exec manipulate and branch pseudos. - switch (MI.getIntrinsicID()) { - case Intrinsic::amdgcn_if: { + auto IntrID = MI.getIntrinsicID(); + switch (IntrID) { + case Intrinsic::amdgcn_if: + case Intrinsic::amdgcn_else: { if (MachineInstr *BrCond = verifyCFIntrinsic(MI, MRI)) { const SIRegisterInfo *TRI = static_cast<const SIRegisterInfo *>(MRI.getTargetRegisterInfo()); @@ -2304,10 +2306,19 @@ bool AMDGPULegalizerInfo::legalizeIntrinsic(MachineInstr &MI, B.setInstr(*BrCond); Register Def = MI.getOperand(1).getReg(); Register Use = MI.getOperand(3).getReg(); - B.buildInstr(AMDGPU::SI_IF) - .addDef(Def) - .addUse(Use) - .addMBB(BrCond->getOperand(1).getMBB()); + + if (IntrID == Intrinsic::amdgcn_if) { + B.buildInstr(AMDGPU::SI_IF) + .addDef(Def) + .addUse(Use) + .addMBB(BrCond->getOperand(1).getMBB()); + } else { + B.buildInstr(AMDGPU::SI_ELSE) + .addDef(Def) + .addUse(Use) + .addMBB(BrCond->getOperand(1).getMBB()) + .addImm(0); + } MRI.setRegClass(Def, TRI->getWaveMaskRegClass()); MRI.setRegClass(Use, TRI->getWaveMaskRegClass()); diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-brcond.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-brcond.mir index d9574afe329..26f562c30fb 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-brcond.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-brcond.mir @@ -97,6 +97,37 @@ body: | ... --- +name: brcond_si_else +body: | + ; WAVE64-LABEL: name: brcond_si_else + ; WAVE64: bb.0: + ; WAVE64: successors: %bb.1(0x80000000) + ; WAVE64: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 + ; WAVE64: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 + ; WAVE64: [[ICMP:%[0-9]+]]:sreg_64_xexec(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]] + ; WAVE64: [[SI_ELSE:%[0-9]+]]:sreg_64_xexec(s64) = SI_ELSE [[ICMP]](s1), %bb.1, 0, implicit-def $exec, implicit-def $scc, implicit $exec + ; WAVE64: bb.1: + ; WAVE32-LABEL: name: brcond_si_else + ; WAVE32: bb.0: + ; WAVE32: successors: %bb.1(0x80000000) + ; WAVE32: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 + ; WAVE32: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 + ; WAVE32: [[ICMP:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]] + ; WAVE32: [[SI_ELSE:%[0-9]+]]:sreg_32_xm0_xexec(s64) = SI_ELSE [[ICMP]](s1), %bb.1, 0, implicit-def $exec, implicit-def $scc, implicit $exec + ; WAVE32: bb.1: + bb.0: + successors: %bb.1 + liveins: $vgpr0, $vgpr1 + %0:_(s32) = COPY $vgpr0 + %1:_(s32) = COPY $vgpr1 + %2:_(s1) = G_ICMP intpred(ne), %0, %1 + %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.else), %2 + G_BRCOND %3, %bb.1 + + bb.1: +... + +--- name: brcond_si_loop body: | ; WAVE64-LABEL: name: brcond_si_loop |
