summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorJim Grosbach <grosbach@apple.com>2009-09-29 17:24:37 +0000
committerJim Grosbach <grosbach@apple.com>2009-09-29 17:24:37 +0000
commit8fc22227bb816546df85a78b6acba0dc975d0786 (patch)
tree2c4c36afb2ada1f5ff4b8ebc0a9dea3bb6a37577
parentbef958c7162dd715c5ef237d28b3b97de6352ef4 (diff)
downloadbcm5719-llvm-8fc22227bb816546df85a78b6acba0dc975d0786.tar.gz
bcm5719-llvm-8fc22227bb816546df85a78b6acba0dc975d0786.zip
Moving register scavenging to a post pass results in virtual registers in
the instruction we're scavenging for. The scavenger needs to know to avoid them when analyzing register usage. llvm-svn: 83077
-rw-r--r--llvm/lib/CodeGen/RegisterScavenging.cpp5
1 files changed, 3 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/RegisterScavenging.cpp b/llvm/lib/CodeGen/RegisterScavenging.cpp
index f878eaa55e6..ada7b4665d3 100644
--- a/llvm/lib/CodeGen/RegisterScavenging.cpp
+++ b/llvm/lib/CodeGen/RegisterScavenging.cpp
@@ -241,7 +241,8 @@ unsigned RegScavenger::findSurvivorReg(MachineBasicBlock::iterator MI,
// Remove any candidates touched by instruction.
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
- if (!MO.isReg() || MO.isUndef() || !MO.getReg())
+ if (!MO.isReg() || MO.isUndef() || !MO.getReg() ||
+ TRI->isVirtualRegister(MO.getReg()))
continue;
Candidates.reset(MO.getReg());
for (const unsigned *R = TRI->getAliasSet(MO.getReg()); *R; R++)
@@ -279,7 +280,7 @@ unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
// Exclude all the registers being used by the instruction.
for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
MachineOperand &MO = I->getOperand(i);
- if (MO.isReg())
+ if (MO.isReg() && !TRI->isVirtualRegister(MO.getReg()))
Candidates.reset(MO.getReg());
}
OpenPOWER on IntegriCloud