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authorDiana Picus <diana.picus@linaro.org>2017-12-18 13:22:28 +0000
committerDiana Picus <diana.picus@linaro.org>2017-12-18 13:22:28 +0000
commit8ee540c01a84db7a9640b5c8e8953a5209d02de6 (patch)
tree18d5706d1fe7f1504f6bb7c621cdee42e3cc1349
parentbc8fdaaf60fd294291868dacabbb6bd83f0c8d32 (diff)
downloadbcm5719-llvm-8ee540c01a84db7a9640b5c8e8953a5209d02de6.tar.gz
bcm5719-llvm-8ee540c01a84db7a9640b5c8e8953a5209d02de6.zip
[ARM GlobalISel] Fix G_(UN)MERGE_VALUES handling after r319524
r319524 has made more G_MERGE_VALUES/G_UNMERGE_VALUES pairs legal than are supported by the rest of the pipeline. Restrict that to only the cases that we can currently handle: packing 32-bit values into 64-bit ones, when we have hardware FP. llvm-svn: 320980
-rw-r--r--llvm/lib/Target/ARM/ARMLegalizerInfo.cpp14
1 files changed, 5 insertions, 9 deletions
diff --git a/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp b/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
index ddcdb1ff42f..2dd1dff64e8 100644
--- a/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
@@ -158,6 +158,11 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) {
setAction({G_FCMP, s1}, Legal);
setAction({G_FCMP, 1, s32}, Legal);
setAction({G_FCMP, 1, s64}, Legal);
+
+ setAction({G_MERGE_VALUES, s64}, Legal);
+ setAction({G_MERGE_VALUES, 1, s32}, Legal);
+ setAction({G_UNMERGE_VALUES, s32}, Legal);
+ setAction({G_UNMERGE_VALUES, 1, s64}, Legal);
} else {
for (unsigned BinOp : {G_FADD, G_FSUB, G_FMUL, G_FDIV})
for (auto Ty : {s32, s64})
@@ -177,15 +182,6 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) {
for (auto Ty : {s32, s64})
setAction({Op, Ty}, Libcall);
- // Merge/Unmerge
- for (const auto &Ty : {s32, s64}) {
- setAction({G_MERGE_VALUES, Ty}, Legal);
- setAction({G_UNMERGE_VALUES, 1, Ty}, Legal);
- }
- for (const auto &Ty : {s16, s32}) {
- setAction({G_MERGE_VALUES, 1, Ty}, Legal);
- setAction({G_UNMERGE_VALUES, Ty}, Legal);
- }
computeTables();
}
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