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| author | Evan Cheng <evan.cheng@apple.com> | 2009-07-02 23:16:11 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2009-07-02 23:16:11 +0000 |
| commit | 8ecd7eb3f7bcf7cba0e6788fe4b9b255a59c2ffc (patch) | |
| tree | be56f14a92b124be33a618fbb000b157ab2b3e0b | |
| parent | 200e0757c7411bd9ddf6ec17672f9f7bc27ffa4f (diff) | |
| download | bcm5719-llvm-8ecd7eb3f7bcf7cba0e6788fe4b9b255a59c2ffc.tar.gz bcm5719-llvm-8ecd7eb3f7bcf7cba0e6788fe4b9b255a59c2ffc.zip | |
Sign extending pre/post indexed loads.
llvm-svn: 74736
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp | 12 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrThumb2.td | 22 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Thumb2/thumb2-ldr_pre.ll | 11 |
3 files changed, 42 insertions, 3 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp index 4b73ba21d74..6485fc1d360 100644 --- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -794,6 +794,7 @@ SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDValue Op) { return NULL; MVT LoadedVT = LD->getMemoryVT(); + bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD; SDValue Offset; bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC); unsigned Opcode = 0; @@ -804,10 +805,17 @@ SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDValue Op) { Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST; break; case MVT::i16: - Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST; + if (isSExtLd) + Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST; + else + Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST; break; case MVT::i8: - Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST; + case MVT::i1: + if (isSExtLd) + Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST; + else + Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST; break; default: return NULL; diff --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td index 127b274072e..e418a4f7163 100644 --- a/llvm/lib/Target/ARM/ARMInstrThumb2.td +++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td @@ -579,6 +579,28 @@ def t2LDRH_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), "ldrh", " $dst, [$base], $offset", "$base = $base_wb", []>; +def t2LDRSB_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), + (ins t2addrmode_imm8:$addr), + AddrModeT2_i8, IndexModePre, + "ldrsb", " $dst, $addr!", "$addr.base = $base_wb", + []>; +def t2LDRSB_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), + (ins GPR:$base, t2am_imm8_offset:$offset), + AddrModeT2_i8, IndexModePost, + "ldrsb", " $dst, [$base], $offset", "$base = $base_wb", + []>; + +def t2LDRSH_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), + (ins t2addrmode_imm8:$addr), + AddrModeT2_i8, IndexModePre, + "ldrsh", " $dst, $addr!", "$addr.base = $base_wb", + []>; +def t2LDRSH_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), + (ins GPR:$base, t2am_imm8_offset:$offset), + AddrModeT2_i8, IndexModePost, + "ldrsh", " $dst, [$base], $offset", "$base = $base_wb", + []>; + // Store defm t2STR : T2I_st<"str", BinOpFrag<(store node:$LHS, node:$RHS)>>; defm t2STRB : T2I_st<"strb", BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>; diff --git a/llvm/test/CodeGen/Thumb2/thumb2-ldr_pre.ll b/llvm/test/CodeGen/Thumb2/thumb2-ldr_pre.ll index 7738fd74d37..f773e6331bf 100644 --- a/llvm/test/CodeGen/Thumb2/thumb2-ldr_pre.ll +++ b/llvm/test/CodeGen/Thumb2/thumb2-ldr_pre.ll @@ -1,5 +1,7 @@ ; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | \ -; RUN: grep {ldr.*\\!} | count 2 +; RUN: grep {ldr.*\\!} | count 3 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | \ +; RUN: grep {ldrsb.*\\!} | count 1 define i32* @test1(i32* %X, i32* %dest) { %Y = getelementptr i32* %X, i32 4 ; <i32*> [#uses=2] @@ -17,3 +19,10 @@ define i32 @test2(i32 %a, i32 %b) { ret i32 %tmp5 } +define i8* @test3(i8* %X, i32* %dest) { + %tmp1 = getelementptr i8* %X, i32 4 + %tmp2 = load i8* %tmp1 + %tmp3 = sext i8 %tmp2 to i32 + store i32 %tmp3, i32* %dest + ret i8* %tmp1 +} |
