Tidy up ValueType names in comments.

llvm-svn: 37688

2 files changed, 5 insertions, 5 deletions

diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index eb81d54a9a9..0584d6ed6e6 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -5649,8 +5649,8 @@ void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
 
 
 /// PackVectorOp - Given an operand of MVT::Vector type, convert it into the
-/// equivalent operation that returns a scalar (e.g. F32) or packed value
-/// (e.g. MVT::V4F32).  When this is called, we know that PackedVT is the right
+/// equivalent operation that returns a scalar (e.g. MVT::f32) or packed value
+/// (e.g. MVT::v4f32).  When this is called, we know that PackedVT is the right
 /// type for the result.
 SDOperand SelectionDAGLegalize::PackVectorOp(SDOperand Op, 
                                              MVT::ValueType NewVT) {
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index f5bb9c7ee55..caedf5745d1 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -243,10 +243,10 @@ void TargetLowering::computeRegisterProperties() {
     else
       TransformToType[(MVT::ValueType)IntReg] = (MVT::ValueType)IntReg;
 
-  // If the target does not have native F64 support, expand it to I64. We will
+  // If the target does not have native f64 support, expand it to i64. We will
   // be generating soft float library calls. If the target does not have native
-  // support for F32, promote it to F64 if it is legal. Otherwise, expand it to
-  // I32.
+  // support for f32, promote it to f64 if it is legal. Otherwise, expand it to
+  // i32.
   if (isTypeLegal(MVT::f64))
     TransformToType[MVT::f64] = MVT::f64;  
   else {