[mips][microMIPS] Add R_MICROMIPS_PC18_S3 relocation

Differential Revision: http://reviews.llvm.org/D15026

llvm-svn: 267130

6 files changed, 32 insertions, 2 deletions

diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
index d3d43c16056..6abf5e78545 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
@@ -143,6 +143,19 @@ static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
       return 0;
     }
     break;
+  case Mips::fixup_MICROMIPS_PC18_S3:
+    // Check alignment.
+    if ((Value & 7) && Ctx) {
+      Ctx->reportError(Fixup.getLoc(), "out of range PC18 fixup");
+    }
+    // Forcing a signed division because Value can be negative.
+    Value = (int64_t)Value / 8;
+    // We now check if Value can be encoded as a 18-bit signed immediate.
+    if (!isInt<18>(Value) && Ctx) {
+      Ctx->reportError(Fixup.getLoc(), "out of range PC18 fixup");
+      return 0;
+    }
+    break;
   case Mips::fixup_MIPS_PC21_S2:
     // Forcing a signed division because Value can be negative.
     Value = (int64_t) Value / 4;
@@ -324,6 +337,7 @@ getFixupKindInfo(MCFixupKind Kind) const {
     { "fixup_MICROMIPS_PC16_S1", 0,     16,   MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MICROMIPS_PC26_S1", 0,     26,   MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MICROMIPS_PC19_S2", 0,     19,   MCFixupKindInfo::FKF_IsPCRel },
+    { "fixup_MICROMIPS_PC18_S3", 0,     18,   MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MICROMIPS_CALL16",  0,     16,   0 },
     { "fixup_MICROMIPS_GOT_DISP",        0,     16,   0 },
     { "fixup_MICROMIPS_GOT_PAGE",        0,     16,   0 },
@@ -392,6 +406,7 @@ getFixupKindInfo(MCFixupKind Kind) const {
     { "fixup_MICROMIPS_PC16_S1",16,     16,   MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MICROMIPS_PC26_S1", 6,     26,   MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MICROMIPS_PC19_S2",13,     19,   MCFixupKindInfo::FKF_IsPCRel },
+    { "fixup_MICROMIPS_PC18_S3",14,     18,   MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MICROMIPS_CALL16", 16,     16,   0 },
     { "fixup_MICROMIPS_GOT_DISP",        16,     16,   0 },
     { "fixup_MICROMIPS_GOT_PAGE",        16,     16,   0 },
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp
index 7aee53162d8..cdb5c89d3ec 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp
@@ -93,6 +93,8 @@ unsigned MipsELFObjectWriter::getRelocType(MCContext &Ctx,
       return ELF::R_MICROMIPS_PC26_S1;
     case Mips::fixup_MICROMIPS_PC19_S2:
       return ELF::R_MICROMIPS_PC19_S2;
+    case Mips::fixup_MICROMIPS_PC18_S3:
+      return ELF::R_MICROMIPS_PC18_S3;
     case Mips::fixup_MIPS_PC19_S2:
       return ELF::R_MIPS_PC19_S2;
     case Mips::fixup_MIPS_PC18_S3:
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h b/llvm/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h
index c718df77547..ba6038e0fed 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h
@@ -176,6 +176,9 @@ namespace Mips {
     // resulting in - R_MICROMIPS_PC19_S2
     fixup_MICROMIPS_PC19_S2,
 
+    // resulting in - R_MICROMIPS_PC18_S3
+    fixup_MICROMIPS_PC18_S3,
+
     // resulting in - R_MICROMIPS_CALL16
     fixup_MICROMIPS_CALL16,
 
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
index 15738da378a..2d17309cbe1 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
@@ -899,8 +899,9 @@ MipsMCCodeEmitter::getSimm18Lsl3Encoding(const MCInst &MI, unsigned OpNo,
          "getSimm18Lsl2Encoding expects only expressions or an immediate");
 
   const MCExpr *Expr = MO.getExpr();
-  Fixups.push_back(MCFixup::create(0, Expr,
-                                   MCFixupKind(Mips::fixup_MIPS_PC18_S3)));
+  Mips::Fixups FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_PC18_S3
+                                            : Mips::fixup_MIPS_PC18_S3;
+  Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(FixupKind)));
   return 0;
 }
 
diff --git a/llvm/test/MC/Mips/micromips32r6/relocations.s b/llvm/test/MC/Mips/micromips32r6/relocations.s
index 98123ef8f9e..0fb1ef882b7 100644
--- a/llvm/test/MC/Mips/micromips32r6/relocations.s
+++ b/llvm/test/MC/Mips/micromips32r6/relocations.s
@@ -23,6 +23,8 @@
 # CHECK-ELF: Relocations [
 # CHECK-ELF:     0x0 R_MICROMIPS_PC26_S1 bar 0x0
 # CHECK-ELF:     0x4 R_MICROMIPS_PC26_S1 bar 0x0
+# CHECK-ELF:     0x8 R_MICROMIPS_PC19_S2 bar 0x0
+# CHECK-ELF:     0xC R_MICROMIPS_PC19_S2 bar 0x0
 # CHECK-ELF: ]
 
   balc  bar
diff --git a/llvm/test/MC/Mips/micromips64r6/relocations.s b/llvm/test/MC/Mips/micromips64r6/relocations.s
index 0963e830d9b..fc1ffbfbeed 100644
--- a/llvm/test/MC/Mips/micromips64r6/relocations.s
+++ b/llvm/test/MC/Mips/micromips64r6/relocations.s
@@ -17,15 +17,22 @@
 # CHECK-FIXUP: lwpc    $2,  bar # encoding: [0x78,0b01001AAA,A,A]
 # CHECK-FIXUP:                  #   fixup A - offset: 0,
 # CHECK-FIXUP:                      value: bar, kind: fixup_MICROMIPS_PC19_S2
+# CHECK-FIXUP: ldpc  $2, bar    # encoding: [0x78,0b010110AA,A,A]
+# CHECK-FIXUP:                  #   fixup A - offset: 0,
+# CHECK-FIXUP:                      value: bar, kind: fixup_MICROMIPS_PC18_S3
 #------------------------------------------------------------------------------
 # Check that the appropriate relocations were created.
 #------------------------------------------------------------------------------
 # CHECK-ELF: Relocations [
 # CHECK-ELF:     0x0 R_MICROMIPS_PC26_S1 bar 0x0
 # CHECK-ELF:     0x4 R_MICROMIPS_PC26_S1 bar 0x0
+# CHECK-ELF:     0x8 R_MICROMIPS_PC19_S2 bar 0x0
+# CHECK-ELF:     0xC R_MICROMIPS_PC19_S2 bar 0x0
+# CHECK-ELF:     0x10 R_MICROMIPS_PC18_S3 bar 0x0
 # CHECK-ELF: ]
 
   balc  bar
   bc    bar
   addiupc $2,bar
   lwpc    $2,bar
+  ldpc  $2, bar