[mips] Implement tlbp, tlbr, tlbwi, and tlbwr

Reviewers: vmedic, dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D3571

llvm-svn: 208301

20 files changed, 52 insertions, 36 deletions

diff --git a/llvm/lib/Target/Mips/MipsInstrFormats.td b/llvm/lib/Target/Mips/MipsInstrFormats.td
index 4afc327f7f2..0377eabed78 100644
--- a/llvm/lib/Target/Mips/MipsInstrFormats.td
+++ b/llvm/lib/Target/Mips/MipsInstrFormats.td
@@ -843,3 +843,12 @@ class BARRIER_FM<bits<5> op> : StdArch {
   let Inst{10-6} = op; // Operation
   let Inst{5-0} = 0;   // SLL
 }
+
+class COP0_TLB_FM<bits<6> op> : StdArch {
+  bits<32> Inst;
+
+  let Inst{31-26} = 0x10; // COP0
+  let Inst{25} = 1;       // CO
+  let Inst{24-6} = 0;
+  let Inst{5-0} = op;     // Operation
+}
diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td
index 4c3e2e39d5f..d9d137b0030 100644
--- a/llvm/lib/Target/Mips/MipsInstrInfo.td
+++ b/llvm/lib/Target/Mips/MipsInstrInfo.td
@@ -1207,6 +1207,13 @@ def SSNOP : Barrier<"ssnop">, BARRIER_FM<1>;
 def EHB : Barrier<"ehb">, BARRIER_FM<3>;
 def PAUSE : Barrier<"pause">, BARRIER_FM<5>, ISA_MIPS32R2;
 
+class TLB<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
+                                      FrmOther>;
+def TLBP : TLB<"tlbp">, COP0_TLB_FM<0x08>;
+def TLBR : TLB<"tlbr">, COP0_TLB_FM<0x01>;
+def TLBWI : TLB<"tlbwi">, COP0_TLB_FM<0x02>;
+def TLBWR : TLB<"tlbwr">, COP0_TLB_FM<0x06>;
+
 //===----------------------------------------------------------------------===//
 // Instruction aliases
 //===----------------------------------------------------------------------===//
diff --git a/llvm/test/MC/Mips/mips1/valid-xfail.s b/llvm/test/MC/Mips/mips1/valid-xfail.s
index 784338cc371..a970a91ecc8 100644
--- a/llvm/test/MC/Mips/mips1/valid-xfail.s
+++ b/llvm/test/MC/Mips/mips1/valid-xfail.s
@@ -7,10 +7,6 @@
 # XFAIL: *
 
 	.set noat
-	tlbp
-	tlbr
-	tlbwi
-	tlbwr
 	lwc0	c0_entrylo,-7321($s2)
 	lwc3	$10,-32265($k0)
 	swc0	c0_prid,18904($s3)
diff --git a/llvm/test/MC/Mips/mips1/valid.s b/llvm/test/MC/Mips/mips1/valid.s
index 4ad74acb537..9d619697cb2 100644
--- a/llvm/test/MC/Mips/mips1/valid.s
+++ b/llvm/test/MC/Mips/mips1/valid.s
@@ -92,4 +92,8 @@
 	swc2	$25,24880($s0)
 	swl	$t7,13694($s3)
 	swr	$s1,-26590($t6)
+	tlbp                       # CHECK: tlbp                   # encoding: [0x42,0x00,0x00,0x08]
+	tlbr                       # CHECK: tlbr                   # encoding: [0x42,0x00,0x00,0x01]
+	tlbwi                      # CHECK: tlbwi                  # encoding: [0x42,0x00,0x00,0x02]
+	tlbwr                      # CHECK: tlbwr                  # encoding: [0x42,0x00,0x00,0x06]
 	xor	$s2,$a0,$s8
diff --git a/llvm/test/MC/Mips/mips2/valid-xfail.s b/llvm/test/MC/Mips/mips2/valid-xfail.s
index e8b8666da6e..9c175b10cce 100644
--- a/llvm/test/MC/Mips/mips2/valid-xfail.s
+++ b/llvm/test/MC/Mips/mips2/valid-xfail.s
@@ -10,7 +10,3 @@
 	ldc3	$29,-28645($s1)
 	lwc3	$10,-32265($k0)
 	sdc3	$12,5835($t2)
-	tlbp
-	tlbr
-	tlbwi
-	tlbwr
diff --git a/llvm/test/MC/Mips/mips2/valid.s b/llvm/test/MC/Mips/mips2/valid.s
index dc4a8b6ea91..8e2331f4e35 100644
--- a/llvm/test/MC/Mips/mips2/valid.s
+++ b/llvm/test/MC/Mips/mips2/valid.s
@@ -109,6 +109,10 @@
 	teqi	$s5,-17504
 	tgei	$s1,5025
 	tgeiu	$sp,-28621
+	tlbp                       # CHECK: tlbp                   # encoding: [0x42,0x00,0x00,0x08]
+	tlbr                       # CHECK: tlbr                   # encoding: [0x42,0x00,0x00,0x01]
+	tlbwi                      # CHECK: tlbwi                  # encoding: [0x42,0x00,0x00,0x02]
+	tlbwr                      # CHECK: tlbwr                  # encoding: [0x42,0x00,0x00,0x06]
 	tlti	$t6,-21059
 	tltiu	$ra,-5076
 	tnei	$t4,-29647
diff --git a/llvm/test/MC/Mips/mips3/valid-xfail.s b/llvm/test/MC/Mips/mips3/valid-xfail.s
index 329dde12a24..c3905715065 100644
--- a/llvm/test/MC/Mips/mips3/valid-xfail.s
+++ b/llvm/test/MC/Mips/mips3/valid-xfail.s
@@ -8,7 +8,3 @@
 
 	.set noat
 	lwc3	$10,-32265($k0)
-	tlbp
-	tlbr
-	tlbwi
-	tlbwr
diff --git a/llvm/test/MC/Mips/mips3/valid.s b/llvm/test/MC/Mips/mips3/valid.s
index 68f97038d4a..d7bae7df2a4 100644
--- a/llvm/test/MC/Mips/mips3/valid.s
+++ b/llvm/test/MC/Mips/mips3/valid.s
@@ -159,6 +159,10 @@
 	teqi	$s5,-17504
 	tgei	$s1,5025
 	tgeiu	$sp,-28621
+	tlbp                       # CHECK: tlbp                   # encoding: [0x42,0x00,0x00,0x08]
+	tlbr                       # CHECK: tlbr                   # encoding: [0x42,0x00,0x00,0x01]
+	tlbwi                      # CHECK: tlbwi                  # encoding: [0x42,0x00,0x00,0x02]
+	tlbwr                      # CHECK: tlbwr                  # encoding: [0x42,0x00,0x00,0x06]
 	tlti	$t6,-21059
 	tltiu	$ra,-5076
 	tnei	$t4,-29647
diff --git a/llvm/test/MC/Mips/mips32/valid-xfail.s b/llvm/test/MC/Mips/mips32/valid-xfail.s
index 65cebd38185..15a4eecee52 100644
--- a/llvm/test/MC/Mips/mips32/valid-xfail.s
+++ b/llvm/test/MC/Mips/mips32/valid-xfail.s
@@ -38,7 +38,3 @@
 	ldc3	$29,-28645($s1)
 	rorv	$t5,$a3,$s5
 	sdc3	$12,5835($t2)
-	tlbp
-	tlbr
-	tlbwi
-	tlbwr
diff --git a/llvm/test/MC/Mips/mips32/valid.s b/llvm/test/MC/Mips/mips32/valid.s
index 2abdd780b33..be31475a9cb 100644
--- a/llvm/test/MC/Mips/mips32/valid.s
+++ b/llvm/test/MC/Mips/mips32/valid.s
@@ -134,6 +134,10 @@
 	teqi	$s5,-17504
 	tgei	$s1,5025
 	tgeiu	$sp,-28621
+	tlbp                       # CHECK: tlbp                   # encoding: [0x42,0x00,0x00,0x08]
+	tlbr                       # CHECK: tlbr                   # encoding: [0x42,0x00,0x00,0x01]
+	tlbwi                      # CHECK: tlbwi                  # encoding: [0x42,0x00,0x00,0x02]
+	tlbwr                      # CHECK: tlbwr                  # encoding: [0x42,0x00,0x00,0x06]
 	tlti	$t6,-21059
 	tltiu	$ra,-5076
 	tnei	$t4,-29647
diff --git a/llvm/test/MC/Mips/mips32r2/valid-xfail.s b/llvm/test/MC/Mips/mips32r2/valid-xfail.s
index 623c7f6cb47..b044e7b8edc 100644
--- a/llvm/test/MC/Mips/mips32r2/valid-xfail.s
+++ b/llvm/test/MC/Mips/mips32r2/valid-xfail.s
@@ -304,10 +304,6 @@
 	tlbgwr
 	tlbinv
 	tlbinvf
-	tlbp
-	tlbr
-	tlbwi
-	tlbwr
 	trunc.l.d	$f23,$f23
 	trunc.l.s	$f28,$f31
 	wrpgpr	$zero,$t5
diff --git a/llvm/test/MC/Mips/mips32r2/valid.s b/llvm/test/MC/Mips/mips32r2/valid.s
index e0cb86d02c9..f7fa2ef8350 100644
--- a/llvm/test/MC/Mips/mips32r2/valid.s
+++ b/llvm/test/MC/Mips/mips32r2/valid.s
@@ -161,6 +161,10 @@
 	teqi	$s5,-17504
 	tgei	$s1,5025
 	tgeiu	$sp,-28621
+	tlbp                       # CHECK: tlbp                   # encoding: [0x42,0x00,0x00,0x08]
+	tlbr                       # CHECK: tlbr                   # encoding: [0x42,0x00,0x00,0x01]
+	tlbwi                      # CHECK: tlbwi                  # encoding: [0x42,0x00,0x00,0x02]
+	tlbwr                      # CHECK: tlbwr                  # encoding: [0x42,0x00,0x00,0x06]
 	tlti	$t6,-21059
 	tltiu	$ra,-5076
 	tnei	$t4,-29647
diff --git a/llvm/test/MC/Mips/mips4/valid-xfail.s b/llvm/test/MC/Mips/mips4/valid-xfail.s
index 9120943dce2..66de33061ae 100644
--- a/llvm/test/MC/Mips/mips4/valid-xfail.s
+++ b/llvm/test/MC/Mips/mips4/valid-xfail.s
@@ -47,7 +47,3 @@
 	recip.s	$f3,$f30
 	rsqrt.d	$f3,$f28
 	rsqrt.s	$f4,$f8
-	tlbp
-	tlbr
-	tlbwi
-	tlbwr
diff --git a/llvm/test/MC/Mips/mips4/valid.s b/llvm/test/MC/Mips/mips4/valid.s
index 1201346b8d1..426cb4cbc7c 100644
--- a/llvm/test/MC/Mips/mips4/valid.s
+++ b/llvm/test/MC/Mips/mips4/valid.s
@@ -177,6 +177,10 @@
 	teqi	$s5,-17504
 	tgei	$s1,5025
 	tgeiu	$sp,-28621
+	tlbp                       # CHECK: tlbp                   # encoding: [0x42,0x00,0x00,0x08]
+	tlbr                       # CHECK: tlbr                   # encoding: [0x42,0x00,0x00,0x01]
+	tlbwi                      # CHECK: tlbwi                  # encoding: [0x42,0x00,0x00,0x02]
+	tlbwr                      # CHECK: tlbwr                  # encoding: [0x42,0x00,0x00,0x06]
 	tlti	$t6,-21059
 	tltiu	$ra,-5076
 	tnei	$t4,-29647
diff --git a/llvm/test/MC/Mips/mips5/valid-xfail.s b/llvm/test/MC/Mips/mips5/valid-xfail.s
index 3c211d6c05d..997e949ae21 100644
--- a/llvm/test/MC/Mips/mips5/valid-xfail.s
+++ b/llvm/test/MC/Mips/mips5/valid-xfail.s
@@ -85,7 +85,3 @@
 	rsqrt.d	$f3,$f28
 	rsqrt.s	$f4,$f8
 	sub.ps	$f5,$f14,$f26
-	tlbp
-	tlbr
-	tlbwi
-	tlbwr
diff --git a/llvm/test/MC/Mips/mips5/valid.s b/llvm/test/MC/Mips/mips5/valid.s
index f82181fd7c8..8a4b5ebca5a 100644
--- a/llvm/test/MC/Mips/mips5/valid.s
+++ b/llvm/test/MC/Mips/mips5/valid.s
@@ -177,6 +177,10 @@
 	teqi	$s5,-17504
 	tgei	$s1,5025
 	tgeiu	$sp,-28621
+	tlbp                       # CHECK: tlbp                   # encoding: [0x42,0x00,0x00,0x08]
+	tlbr                       # CHECK: tlbr                   # encoding: [0x42,0x00,0x00,0x01]
+	tlbwi                      # CHECK: tlbwi                  # encoding: [0x42,0x00,0x00,0x02]
+	tlbwr                      # CHECK: tlbwr                  # encoding: [0x42,0x00,0x00,0x06]
 	tlti	$t6,-21059
 	tltiu	$ra,-5076
 	tnei	$t4,-29647
diff --git a/llvm/test/MC/Mips/mips64/valid-xfail.s b/llvm/test/MC/Mips/mips64/valid-xfail.s
index 61bf0607513..610cdf796c7 100644
--- a/llvm/test/MC/Mips/mips64/valid-xfail.s
+++ b/llvm/test/MC/Mips/mips64/valid-xfail.s
@@ -92,7 +92,3 @@
 	rsqrt.d	$f3,$f28
 	rsqrt.s	$f4,$f8
 	sub.ps	$f5,$f14,$f26
-	tlbp
-	tlbr
-	tlbwi
-	tlbwr
diff --git a/llvm/test/MC/Mips/mips64/valid.s b/llvm/test/MC/Mips/mips64/valid.s
index 175a317055d..2164e2c151a 100644
--- a/llvm/test/MC/Mips/mips64/valid.s
+++ b/llvm/test/MC/Mips/mips64/valid.s
@@ -191,6 +191,10 @@
 	teqi	$s5,-17504
 	tgei	$s1,5025
 	tgeiu	$sp,-28621
+	tlbp                       # CHECK: tlbp                   # encoding: [0x42,0x00,0x00,0x08]
+	tlbr                       # CHECK: tlbr                   # encoding: [0x42,0x00,0x00,0x01]
+	tlbwi                      # CHECK: tlbwi                  # encoding: [0x42,0x00,0x00,0x02]
+	tlbwr                      # CHECK: tlbwr                  # encoding: [0x42,0x00,0x00,0x06]
 	tlti	$t6,-21059
 	tltiu	$ra,-5076
 	tnei	$t4,-29647
diff --git a/llvm/test/MC/Mips/mips64r2/valid-xfail.s b/llvm/test/MC/Mips/mips64r2/valid-xfail.s
index be691b16189..1bb5ac9f671 100644
--- a/llvm/test/MC/Mips/mips64r2/valid-xfail.s
+++ b/llvm/test/MC/Mips/mips64r2/valid-xfail.s
@@ -306,10 +306,6 @@
 	tlbgwr
 	tlbinv
 	tlbinvf
-	tlbp
-	tlbr
-	tlbwi
-	tlbwr
 	wrpgpr	$zero,$t5
 	xor.v	$w20,$w21,$w30
 	yield	$v1,$s0
diff --git a/llvm/test/MC/Mips/mips64r2/valid.s b/llvm/test/MC/Mips/mips64r2/valid.s
index 86ed004dd78..a136fc47cbe 100644
--- a/llvm/test/MC/Mips/mips64r2/valid.s
+++ b/llvm/test/MC/Mips/mips64r2/valid.s
@@ -213,6 +213,10 @@
 	teqi	$s5,-17504
 	tgei	$s1,5025
 	tgeiu	$sp,-28621
+	tlbp                       # CHECK: tlbp                   # encoding: [0x42,0x00,0x00,0x08]
+	tlbr                       # CHECK: tlbr                   # encoding: [0x42,0x00,0x00,0x01]
+	tlbwi                      # CHECK: tlbwi                  # encoding: [0x42,0x00,0x00,0x02]
+	tlbwr                      # CHECK: tlbwr                  # encoding: [0x42,0x00,0x00,0x06]
 	tlti	$t6,-21059
 	tltiu	$ra,-5076
 	tnei	$t4,-29647