ARM assembly parsing of MUL instruction.

Correctly handle 's' bit and predication suffices. Add parsing and encoding
tests.

llvm-svn: 135596

2 files changed, 16 insertions, 1 deletions

diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 0cf9a4a042e..89501dc0888 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -1977,7 +1977,8 @@ StringRef ARMAsmParser::SplitMnemonic(StringRef Mnemonic,
 
   // First, split out any predication code. Ignore mnemonics we know aren't
   // predicated but do have a carry-set and so weren't caught above.
-  if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs") {
+  if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
+      Mnemonic != "muls") {
     unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
       .Case("eq", ARMCC::EQ)
       .Case("ne", ARMCC::NE)
diff --git a/llvm/test/MC/ARM/basic-arm-instructions.s b/llvm/test/MC/ARM/basic-arm-instructions.s
index 00cfec9c7e6..9fb90d23ee4 100644
--- a/llvm/test/MC/ARM/basic-arm-instructions.s
+++ b/llvm/test/MC/ARM/basic-arm-instructions.s
@@ -812,6 +812,20 @@ _func:
 @ CHECK: msr  CPSR_fsxc, r0 @ encoding: [0x00,0xf0,0x2f,0xe1]
 
 @------------------------------------------------------------------------------
+@ MUL
+@------------------------------------------------------------------------------
+
+  mul r5, r6, r7
+  muls r5, r6, r7
+  mulgt r5, r6, r7
+  mulsle r5, r6, r7
+
+@ CHECK: mul	r5, r6, r7              @ encoding: [0x96,0x07,0x05,0xe0]
+@ CHECK: muls	r5, r6, r7              @ encoding: [0x96,0x07,0x15,0xe0]
+@ CHECK: mulgt	r5, r6, r7              @ encoding: [0x96,0x07,0x05,0xc0]
+@ CHECK: mulsle	r5, r6, r7              @ encoding: [0x96,0x07,0x15,0xd0]
+
+@------------------------------------------------------------------------------
 @ STM*
 @------------------------------------------------------------------------------
         stm       r2, {r1,r3-r6,sp}