ARM vector compare to zero instruction assembly parsing support.

llvm-svn: 137389

2 files changed, 15 insertions, 7 deletions

diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 07570ae8e20..13a7f0b9024 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -2865,6 +2865,21 @@ bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
     Operands.erase(Operands.begin() + 1);
     delete Op;
   }
+
+  // The vector-compare-to-zero instructions have a literal token "#0" at
+  // the end that comes to here as an immediate operand. Convert it to a
+  // token to play nicely with the matcher.
+  if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" ||
+      Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 &&
+      static_cast<ARMOperand*>(Operands[5])->isImm()) {
+    ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
+    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
+    if (CE && CE->getValue() == 0) {
+      Operands.erase(Operands.begin() + 5);
+      Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
+      delete Op;
+    }
+  }
   return false;
 }
 
diff --git a/llvm/test/MC/ARM/neon-cmp-encoding.s b/llvm/test/MC/ARM/neon-cmp-encoding.s
index 6bfc549e947..4933e720347 100644
--- a/llvm/test/MC/ARM/neon-cmp-encoding.s
+++ b/llvm/test/MC/ARM/neon-cmp-encoding.s
@@ -1,11 +1,4 @@
 @ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s
-@ XFAIL: *
-
-@ FIXME: We cannot currently test the following instructions, which are 
-@ currently marked as for-disassembly only in the .td files:
-@  - VCEQz
-@  - VCGEz, VCLEz
-@  - VCGTz, VCLTz
 
 @ CHECK: vceq.i8	d16, d16, d17           @ encoding: [0xb1,0x08,0x40,0xf3]
 	vceq.i8	d16, d16, d17