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| author | Tom Stellard <tstellar@redhat.com> | 2017-06-06 14:16:50 +0000 |
|---|---|---|
| committer | Tom Stellard <tstellar@redhat.com> | 2017-06-06 14:16:50 +0000 |
| commit | 8cd60a506781db87bd996768b69fef8865d0f2a6 (patch) | |
| tree | a6435302baad3b423c6ce066392e07549cff6567 | |
| parent | 32f29fac41f0bfa331bbb77c3dbc6d22a9647387 (diff) | |
| download | bcm5719-llvm-8cd60a506781db87bd996768b69fef8865d0f2a6.tar.gz bcm5719-llvm-8cd60a506781db87bd996768b69fef8865d0f2a6.zip | |
AMDGPU/GlobalISel: Mark 32-bit G_ICMP as legal
Reviewers: arsenm
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D33890
llvm-svn: 304797
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 3 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir | 24 |
2 files changed, 27 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp index fa259602d48..4fdc270201e 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp @@ -47,6 +47,9 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo() { setAction({G_GEP, P2}, Legal); setAction({G_GEP, 1, S64}, Legal); + setAction({G_ICMP, S1}, Legal); + setAction({G_ICMP, 1, S32}, Legal); + setAction({G_LOAD, P1}, Legal); setAction({G_LOAD, P2}, Legal); setAction({G_LOAD, S32}, Legal); diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir new file mode 100644 index 00000000000..ebd473d769b --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir @@ -0,0 +1,24 @@ +# RUN: llc -O0 -march=amdgcn -mcpu=fiji -run-pass=legalizer -global-isel %s -o - | FileCheck %s + +--- | + define void @test_icmp() { + entry: + ret void + } +... + +--- +name: test_icmp +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +body: | + bb.0.entry: + liveins: %vgpr0 + %0(s32) = G_CONSTANT i32 0 + %1(s32) = COPY %vgpr0 + + ; CHECK: %2(s1) = G_ICMP intpred(ne), %0(s32), %1 + %2(s1) = G_ICMP intpred(ne), %0, %1 +... |
