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| author | Marina Yatsina <marina.yatsina@intel.com> | 2015-08-11 12:05:06 +0000 |
|---|---|---|
| committer | Marina Yatsina <marina.yatsina@intel.com> | 2015-08-11 12:05:06 +0000 |
| commit | 8c997af1036f18f469800c72493bb821547c6f32 (patch) | |
| tree | 13046744d00ade286a1f6de85a8588edc4e20a39 | |
| parent | 795daa2e8fb6c4322c3a47ce88a7b20a4135820f (diff) | |
| download | bcm5719-llvm-8c997af1036f18f469800c72493bb821547c6f32.tar.gz bcm5719-llvm-8c997af1036f18f469800c72493bb821547c6f32.zip | |
[X86] Add SAL mnemonics for Intel syntax
SAL and SHL instructions perform the same operation
Differential Revision: http://reviews.llvm.org/D11882
llvm-svn: 244588
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrInfo.td | 1 | ||||
| -rw-r--r-- | llvm/test/MC/X86/intel-syntax.s | 3 |
2 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td index fff094ddf43..d626e078110 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.td +++ b/llvm/lib/Target/X86/X86InstrInfo.td @@ -2548,6 +2548,7 @@ def : MnemonicAlias<"ret", "retw", "att">, Requires<[In16BitMode]>; def : MnemonicAlias<"ret", "retl", "att">, Requires<[In32BitMode]>; def : MnemonicAlias<"ret", "retq", "att">, Requires<[In64BitMode]>; +def : MnemonicAlias<"sal", "shl", "intel">; def : MnemonicAlias<"salb", "shlb", "att">; def : MnemonicAlias<"salw", "shlw", "att">; def : MnemonicAlias<"sall", "shll", "att">; diff --git a/llvm/test/MC/X86/intel-syntax.s b/llvm/test/MC/X86/intel-syntax.s index 8be9642bc5c..ae221bdfcef 100644 --- a/llvm/test/MC/X86/intel-syntax.s +++ b/llvm/test/MC/X86/intel-syntax.s @@ -701,3 +701,6 @@ repnz cmpsb // CHECK: cmpsb %es:(%rdi), (%rsi) // CHECK: repne // CHECK: cmpsb %es:(%rdi), (%rsi) + +sal eax, 123 +// CHECK: shll $123, %eax |
