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| author | Craig Topper <craig.topper@intel.com> | 2019-01-31 00:04:46 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2019-01-31 00:04:46 +0000 |
| commit | 8bdc203d4b2ddab14d8b2a60156aba326ad59d94 (patch) | |
| tree | aabb3bdfcec91303b0d01bb5bde657a64daa9aa7 | |
| parent | e55f6a403972041d5b33188679d059fe6ae6cae1 (diff) | |
| download | bcm5719-llvm-8bdc203d4b2ddab14d8b2a60156aba326ad59d94.tar.gz bcm5719-llvm-8bdc203d4b2ddab14d8b2a60156aba326ad59d94.zip | |
[X86] Remove handling of ISD::INTRINSIC_WO_CHAIN in ReplaceNodeResults.
I believe this was there to handle avx512bw intrinsics that returned i64 type in 32-bit mode. But all those intrinsics have since been changed to v64i1 results or replaced with generic IR.
llvm-svn: 352698
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index fd42dcf1a3c..39fdafede7f 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -1787,7 +1787,6 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM, setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom); if (!Subtarget.is64Bit()) { setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom); - setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom); } // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't @@ -26923,11 +26922,6 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N, return getExtendedControlRegister(N, dl, DAG, Subtarget, Results); } } - case ISD::INTRINSIC_WO_CHAIN: { - if (SDValue V = LowerINTRINSIC_WO_CHAIN(SDValue(N, 0), DAG)) - Results.push_back(V); - return; - } case ISD::READCYCLECOUNTER: { return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget, Results); |

