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| author | Johnny Chen <johnny.chen@apple.com> | 2011-03-24 20:42:48 +0000 |
|---|---|---|
| committer | Johnny Chen <johnny.chen@apple.com> | 2011-03-24 20:42:48 +0000 |
| commit | 8bbc12824a0f6e3367a54966b9f6dc58acf6b15e (patch) | |
| tree | a569c05266ccf0ac90bcd653071cf05d7a6929cc | |
| parent | e01b75cb89edb0d204efd9639adc62347f0db056 (diff) | |
| download | bcm5719-llvm-8bbc12824a0f6e3367a54966b9f6dc58acf6b15e.tar.gz bcm5719-llvm-8bbc12824a0f6e3367a54966b9f6dc58acf6b15e.zip | |
ADR was added with the wrong encoding for inst{24-21}, and the ARM decoder was fooled.
Set the encoding bits to {0,?,?,0}, not 0. Plus delegate the disassembly of ADR to
the more generic ADDri/SUBri instructions, and add a test case for that.
llvm-svn: 128234
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrInfo.td | 2 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/ARM/arm-tests.txt | 3 | ||||
| -rw-r--r-- | llvm/utils/TableGen/ARMDecoderEmitter.cpp | 4 |
3 files changed, 8 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td index 9d09a65da41..cc4fcfc3c89 100644 --- a/llvm/lib/Target/ARM/ARMInstrInfo.td +++ b/llvm/lib/Target/ARM/ARMInstrInfo.td @@ -1253,7 +1253,7 @@ let neverHasSideEffects = 1, isReMaterializable = 1 in // The 'adr' mnemonic encodes differently if the label is before or after // the instruction. The {24-21} opcode bits are set by the fixup, as we don't // know until then which form of the instruction will be used. -def ADR : AI1<0, (outs GPR:$Rd), (ins adrlabel:$label), +def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label), MiscFrm, IIC_iALUi, "adr", "\t$Rd, #$label", []> { bits<4> Rd; bits<12> label; diff --git a/llvm/test/MC/Disassembler/ARM/arm-tests.txt b/llvm/test/MC/Disassembler/ARM/arm-tests.txt index 93d6a03005b..16e6981382e 100644 --- a/llvm/test/MC/Disassembler/ARM/arm-tests.txt +++ b/llvm/test/MC/Disassembler/ARM/arm-tests.txt @@ -1,5 +1,8 @@ # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 | FileCheck %s +# CHECK: addpl r4, pc, #19, 8 +0x4c 0x45 0x8f 0x52 + # CHECK: b #0 0x00 0x00 0x00 0xea diff --git a/llvm/utils/TableGen/ARMDecoderEmitter.cpp b/llvm/utils/TableGen/ARMDecoderEmitter.cpp index 09243e116b3..b174fa961ad 100644 --- a/llvm/utils/TableGen/ARMDecoderEmitter.cpp +++ b/llvm/utils/TableGen/ARMDecoderEmitter.cpp @@ -1584,6 +1584,10 @@ ARMDEBackend::populateInstruction(const CodeGenInstruction &CGI, Name == "MOVr_TC") return false; + // Delegate ADR disassembly to the more generic ADDri/SUBri instructions. + if (Name == "ADR") + return false; + // // The following special cases are for conflict resolutions. // |
