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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-02-02 19:32:42 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-02-02 19:32:42 +0000 |
| commit | 8b175672cbbb19d328038be74fd917e405b46168 (patch) | |
| tree | a036c95a16873ee012fcc32fbe7d7a86c0c468a7 | |
| parent | fb8cdbae0cb246ceca9dfd4dbc8c4a60a2ffe759 (diff) | |
| download | bcm5719-llvm-8b175672cbbb19d328038be74fd917e405b46168.tar.gz bcm5719-llvm-8b175672cbbb19d328038be74fd917e405b46168.zip | |
AMDGPU: Skip promote alloca with no optimizations
llvm-svn: 259551
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/promote-alloca-no-opts.ll | 38 |
3 files changed, 40 insertions, 2 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp b/llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp index 367a9388286..f17317deacb 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp @@ -98,7 +98,7 @@ bool AMDGPUPromoteAlloca::doInitialization(Module &M) { } bool AMDGPUPromoteAlloca::runOnFunction(Function &F) { - if (!TM) + if (!TM || F.hasFnAttribute(Attribute::OptimizeNone)) return false; FunctionType *FTy = F.getFunctionType(); diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp index 82a4cfff37d..ef3a5afb32c 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -229,7 +229,7 @@ void AMDGPUPassConfig::addIRPasses() { void AMDGPUPassConfig::addCodeGenPrepare() { const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine(); const AMDGPUSubtarget &ST = *TM.getSubtargetImpl(); - if (ST.isPromoteAllocaEnabled()) { + if (TM.getOptLevel() > CodeGenOpt::None && ST.isPromoteAllocaEnabled()) { addPass(createAMDGPUPromoteAlloca(&TM)); addPass(createSROAPass()); } diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-no-opts.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-no-opts.ll new file mode 100644 index 00000000000..2cbf0abccdf --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-no-opts.ll @@ -0,0 +1,38 @@ +; RUN: llc -O0 -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mattr=+promote-alloca < %s | FileCheck -check-prefix=NOOPTS -check-prefix=ALL %s +; RUN: llc -O1 -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mattr=+promote-alloca < %s | FileCheck -check-prefix=OPTS -check-prefix=ALL %s + +; ALL-LABEL: {{^}}promote_alloca_i32_array_array: +; NOOPTS: workgroup_group_segment_byte_size = 0{{$}} +; NOOPTS-NOT ds_write +; OPTS: ds_write +define void @promote_alloca_i32_array_array(i32 addrspace(1)* %out, i32 %index) #0 { +entry: + %alloca = alloca [2 x [2 x i32]] + %gep0 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]]* %alloca, i32 0, i32 0, i32 0 + %gep1 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]]* %alloca, i32 0, i32 0, i32 1 + store i32 0, i32* %gep0 + store i32 1, i32* %gep1 + %gep2 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]]* %alloca, i32 0, i32 0, i32 %index + %load = load i32, i32* %gep2 + store i32 %load, i32 addrspace(1)* %out + ret void +} + +; ALL-LABEL: {{^}}optnone_promote_alloca_i32_array_array: +; ALL: workgroup_group_segment_byte_size = 0{{$}} +; ALL-NOT ds_write +define void @optnone_promote_alloca_i32_array_array(i32 addrspace(1)* %out, i32 %index) #1 { +entry: + %alloca = alloca [2 x [2 x i32]] + %gep0 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]]* %alloca, i32 0, i32 0, i32 0 + %gep1 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]]* %alloca, i32 0, i32 0, i32 1 + store i32 0, i32* %gep0 + store i32 1, i32* %gep1 + %gep2 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]]* %alloca, i32 0, i32 0, i32 %index + %load = load i32, i32* %gep2 + store i32 %load, i32 addrspace(1)* %out + ret void +} + +attributes #0 = { nounwind } +attributes #1 = { nounwind optnone noinline } |
