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| author | NAKAMURA Takumi <geek4civic@gmail.com> | 2012-12-19 10:12:48 +0000 |
|---|---|---|
| committer | NAKAMURA Takumi <geek4civic@gmail.com> | 2012-12-19 10:12:48 +0000 |
| commit | 89209462fe7083f4e46013411bf500018754c60a (patch) | |
| tree | 0a9784520615f7684cdf534c7508d168a47f29dd | |
| parent | deee9003ed9909cfab849e4cfae39bbed97d321a (diff) | |
| download | bcm5719-llvm-89209462fe7083f4e46013411bf500018754c60a.tar.gz bcm5719-llvm-89209462fe7083f4e46013411bf500018754c60a.zip | |
X86ISelLowering.cpp: Fix warnings. [-Wlogical-op-parentheses]
llvm-svn: 170523
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index fee9d932e52..93ea3721fe2 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -15934,8 +15934,8 @@ static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG, // TODO: It is possible to support ZExt by zeroing the undef values // during the shuffle phase or after the shuffle. if (RegVT.isVector() && RegVT.isInteger() && - (Ext == ISD::EXTLOAD && Subtarget->hasSSSE3() || - Ext == ISD::SEXTLOAD && Subtarget->hasSSE41())){ + ((Ext == ISD::EXTLOAD && Subtarget->hasSSSE3()) || + (Ext == ISD::SEXTLOAD && Subtarget->hasSSE41()))){ assert(MemVT != RegVT && "Cannot extend to the same type"); assert(MemVT.isVector() && "Must load a vector from memory"); |
