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| author | Quentin Colombet <qcolombet@apple.com> | 2016-04-07 23:10:14 +0000 |
|---|---|---|
| committer | Quentin Colombet <qcolombet@apple.com> | 2016-04-07 23:10:14 +0000 |
| commit | 88f7f6bc4fe7004d62a12cd06ac406cadc4f2f52 (patch) | |
| tree | 8bcaf2107d25f296d4e8156344415b2cc8583f80 | |
| parent | f4e36faa9cadfa88dc22848d96fd2350fa7cc5a4 (diff) | |
| download | bcm5719-llvm-88f7f6bc4fe7004d62a12cd06ac406cadc4f2f52.tar.gz bcm5719-llvm-88f7f6bc4fe7004d62a12cd06ac406cadc4f2f52.zip | |
[AArch64] Fix a typo in the register class to register bank mapping.
For GPR family we want the GPR register bank, not FPR!
llvm-svn: 265743
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp b/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp index 38ede652366..0a7552bc45d 100644 --- a/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp @@ -102,7 +102,7 @@ const RegisterBank &AArch64RegisterBankInfo::getRegBankFromRegClass( case AArch64::tcGPR64RegClassID: case AArch64::WSeqPairsClassRegClassID: case AArch64::XSeqPairsClassRegClassID: - return getRegBank(AArch64::FPRRegBankID); + return getRegBank(AArch64::GPRRegBankID); case AArch64::CCRRegClassID: return getRegBank(AArch64::CCRRegBankID); default: |
