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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2019-03-21 12:41:18 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2019-03-21 12:41:18 +0000 |
| commit | 87d261bfd3f06789b7b9679d8f10fecccbbd328b (patch) | |
| tree | 69c9820453b678fdf6ef40c45b3557af53b533c3 | |
| parent | 361b5b2193421824925a72669f1d06cd63c3d9a7 (diff) | |
| download | bcm5719-llvm-87d261bfd3f06789b7b9679d8f10fecccbbd328b.tar.gz bcm5719-llvm-87d261bfd3f06789b7b9679d8f10fecccbbd328b.zip | |
[Thumb] Fix infinite loop in ABS expansion (PR41160)
Don't expand ISD::ABS node if its legal.
llvm-svn: 356661
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 5 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Thumb/iabs-vector.ll | 20 |
2 files changed, 24 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index be6d11a962a..36df387cd1b 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -10391,9 +10391,12 @@ static SDValue PerformABSCombine(SDNode *N, SelectionDAG &DAG = DCI.DAG; const TargetLowering &TLI = DAG.getTargetLoweringInfo(); - if (!TLI.expandABS(N, res, DAG)) + if (TLI.isOperationLegal(N->getOpcode(), N->getValueType(0))) return SDValue(); + if (!TLI.expandABS(N, res, DAG)) + return SDValue(); + return res; } diff --git a/llvm/test/CodeGen/Thumb/iabs-vector.ll b/llvm/test/CodeGen/Thumb/iabs-vector.ll new file mode 100644 index 00000000000..169400f27ce --- /dev/null +++ b/llvm/test/CodeGen/Thumb/iabs-vector.ll @@ -0,0 +1,20 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=thumbv7--- | FileCheck %s + +define void @PR41160(<8 x i32>* %p) nounwind { +; CHECK-LABEL: PR41160: +; CHECK: @ %bb.0: +; CHECK-NEXT: vld1.8 {d16, d17}, [r0] +; CHECK-NEXT: vabs.s32 q8, q8 +; CHECK-NEXT: vst1.8 {d16, d17}, [r0]! +; CHECK-NEXT: vld1.8 {d16, d17}, [r0] +; CHECK-NEXT: vabs.s32 q8, q8 +; CHECK-NEXT: vst1.8 {d16, d17}, [r0] +; CHECK-NEXT: bx lr + %tmp1 = load <8 x i32>, <8 x i32>* %p, align 1 + %tmp2 = icmp slt <8 x i32> %tmp1, zeroinitializer + %tmp3 = sub nsw <8 x i32> zeroinitializer, %tmp1 + %tmp4 = select <8 x i1> %tmp2, <8 x i32> %tmp3, <8 x i32> %tmp1 + store <8 x i32> %tmp4, <8 x i32>* %p, align 1 + ret void +} |
