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| author | Oliver Stannard <oliver.stannard@arm.com> | 2015-12-09 14:32:11 +0000 |
|---|---|---|
| committer | Oliver Stannard <oliver.stannard@arm.com> | 2015-12-09 14:32:11 +0000 |
| commit | 86f729296ab69755c739bc23f831871929680fbd (patch) | |
| tree | 8e9ea9dae449fa097f83272924245f64b984b9ba | |
| parent | 3c7223133d8fd260fc690dc48d25e9384f9ec322 (diff) | |
| download | bcm5719-llvm-86f729296ab69755c739bc23f831871929680fbd.tar.gz bcm5719-llvm-86f729296ab69755c739bc23f831871929680fbd.zip | |
[AArch64] Fix FP16 vector instructions that should only accept low registers
llvm-svn: 255113
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64InstrFormats.td | 6 | ||||
| -rw-r--r-- | llvm/test/MC/AArch64/fullfp16-diagnostics.s | 40 |
2 files changed, 43 insertions, 3 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td index 101b0f7e1d3..6ac2175e503 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td +++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td @@ -6855,11 +6855,11 @@ multiclass SIMDFPIndexed<bit U, bits<4> opc, string asm, let Predicates = [HasNEON, HasFullFP16] in { def v1i16_indexed : BaseSIMDIndexed<1, U, 1, 0b00, opc, - FPR16Op, FPR16Op, V128, VectorIndexH, + FPR16Op, FPR16Op, V128_lo, VectorIndexH, asm, ".h", "", "", ".h", [(set (f16 FPR16Op:$Rd), (OpNode (f16 FPR16Op:$Rn), - (f16 (vector_extract (v8f16 V128:$Rm), + (f16 (vector_extract (v8f16 V128_lo:$Rm), VectorIndexH:$idx))))]> { bits<3> idx; let Inst{11} = idx{2}; @@ -6995,7 +6995,7 @@ multiclass SIMDFPIndexedTied<bit U, bits<4> opc, string asm> { let Predicates = [HasNEON, HasFullFP16] in { def v1i16_indexed : BaseSIMDIndexedTied<1, U, 1, 0b00, opc, - FPR16Op, FPR16Op, V128, VectorIndexH, + FPR16Op, FPR16Op, V128_lo, VectorIndexH, asm, ".h", "", "", ".h", []> { bits<3> idx; let Inst{11} = idx{2}; diff --git a/llvm/test/MC/AArch64/fullfp16-diagnostics.s b/llvm/test/MC/AArch64/fullfp16-diagnostics.s index 190b6e25a4b..06035dbf702 100644 --- a/llvm/test/MC/AArch64/fullfp16-diagnostics.s +++ b/llvm/test/MC/AArch64/fullfp16-diagnostics.s @@ -40,3 +40,43 @@ // CHECK: error: invalid operand for instruction // CHECK-NEXT: fmulx v2.8h, v3.8h, v17.h[6] // CHECK-NEXT: ^ + + fmla h0, h1, v16.h[3] + fmla h2, h3, v17.h[6] + +// CHECK: error: invalid operand for instruction +// CHECK-NEXT: fmla h0, h1, v16.h[3] +// CHECK-NEXT: ^ +// CHECK: error: invalid operand for instruction +// CHECK-NEXT: fmla h2, h3, v17.h[6] +// CHECK-NEXT: ^ + + fmls h0, h1, v16.h[3] + fmls h2, h3, v17.h[6] + +// CHECK: error: invalid operand for instruction +// CHECK-NEXT: fmls h0, h1, v16.h[3] +// CHECK-NEXT: ^ +// CHECK: error: invalid operand for instruction +// CHECK-NEXT: fmls h2, h3, v17.h[6] +// CHECK-NEXT: ^ + + fmul h0, h1, v16.h[3] + fmul h2, h3, v17.h[6] + +// CHECK: error: invalid operand for instruction +// CHECK-NEXT: fmul h0, h1, v16.h[3] +// CHECK-NEXT: ^ +// CHECK: error: invalid operand for instruction +// CHECK-NEXT: fmul h2, h3, v17.h[6] +// CHECK-NEXT: ^ + + fmulx h0, h1, v16.h[3] + fmulx h2, h3, v17.h[6] + +// CHECK: error: invalid operand for instruction +// CHECK-NEXT: fmulx h0, h1, v16.h[3] +// CHECK-NEXT: ^ +// CHECK: error: invalid operand for instruction +// CHECK-NEXT: fmulx h2, h3, v17.h[6] +// CHECK-NEXT: ^ |
