[AArch64][GlobalISel] Re-enable selection of volatile loads.

We previously disabled this in r323371 because of a bug where we selected an
extending load, but didn't delete the old G_LOAD, resulting in two loads being
generated for volatile loads.

Since we now have dedicated G_SEXTLOAD/G_ZEXTLOAD operations, and that the
tablegen patterns should no longer be able to select (ext(load x)) patterns, it
should be safe to re-enable it.

The old test case should still work as expected.

llvm-svn: 348320

2 files changed, 1 insertions, 7 deletions

diff --git a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
index 46b8b4dc648..fe2727419d5 100644
--- a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
@@ -1013,12 +1013,6 @@ bool AArch64InstructionSelector::select(MachineInstr &I,
     }
     unsigned MemSizeInBits = MemOp.getSize() * 8;
 
-    // FIXME: PR36018: Volatile loads in some cases are incorrectly selected by
-    // folding with an extend. Until we have a G_SEXTLOAD solution bail out if
-    // we hit one.
-    if (Opcode == TargetOpcode::G_LOAD && MemOp.isVolatile())
-      return false;
-
     const unsigned PtrReg = I.getOperand(1).getReg();
 #ifndef NDEBUG
     const RegisterBank &PtrRB = *RBI.getRegBank(PtrReg, MRI, TRI);
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-volatile-load-pr36018.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-volatile-load-pr36018.ll
index 9bda39c9fca..099a9e71e42 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-volatile-load-pr36018.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-volatile-load-pr36018.ll
@@ -3,7 +3,7 @@
 @g = global i16 0, align 2
 declare void @bar(i32)
 
-; Check that only one load is generated. We fall back to
+; Check that only one load is generated for an extending volatile load.
 define hidden void @foo() {
 ; CHECK-NOT: ldrh
 ; CHECK: ldrsh