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| author | Bob Wilson <bob.wilson@apple.com> | 2009-10-21 21:36:27 +0000 |
|---|---|---|
| committer | Bob Wilson <bob.wilson@apple.com> | 2009-10-21 21:36:27 +0000 |
| commit | 854530a7dde65d8dd6af794c41686524fdf8cb80 (patch) | |
| tree | a0da5a5bf6acd54f0c0e65e40518db15594f8c8e | |
| parent | 49914e6eb3f4747e848d45b0d5ad115cb587aa90 (diff) | |
| download | bcm5719-llvm-854530a7dde65d8dd6af794c41686524fdf8cb80.tar.gz bcm5719-llvm-854530a7dde65d8dd6af794c41686524fdf8cb80.zip | |
Most of the NEON shuffle instructions do not support 64-bit element types.
llvm-svn: 84785
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 21 |
1 files changed, 18 insertions, 3 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 8693a8a17b4..6a264fdfc44 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -2361,8 +2361,11 @@ static bool isVREVMask(const SmallVectorImpl<int> &M, EVT VT, assert((BlockSize==16 || BlockSize==32 || BlockSize==64) && "Only possible block sizes for VREV are: 16, 32, 64"); - unsigned NumElts = VT.getVectorNumElements(); unsigned EltSz = VT.getVectorElementType().getSizeInBits(); + if (EltSz == 64) + return false; + + unsigned NumElts = VT.getVectorNumElements(); unsigned BlockElts = M[0] + 1; if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz) @@ -2379,6 +2382,10 @@ static bool isVREVMask(const SmallVectorImpl<int> &M, EVT VT, static bool isVTRNMask(const SmallVectorImpl<int> &M, EVT VT, unsigned &WhichResult) { + unsigned EltSz = VT.getVectorElementType().getSizeInBits(); + if (EltSz == 64) + return false; + unsigned NumElts = VT.getVectorNumElements(); WhichResult = (M[0] == 0 ? 0 : 1); for (unsigned i = 0; i < NumElts; i += 2) { @@ -2391,6 +2398,10 @@ static bool isVTRNMask(const SmallVectorImpl<int> &M, EVT VT, static bool isVUZPMask(const SmallVectorImpl<int> &M, EVT VT, unsigned &WhichResult) { + unsigned EltSz = VT.getVectorElementType().getSizeInBits(); + if (EltSz == 64) + return false; + unsigned NumElts = VT.getVectorNumElements(); WhichResult = (M[0] == 0 ? 0 : 1); for (unsigned i = 0; i != NumElts; ++i) { @@ -2399,7 +2410,7 @@ static bool isVUZPMask(const SmallVectorImpl<int> &M, EVT VT, } // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32. - if (VT.is64BitVector() && VT.getVectorElementType().getSizeInBits() == 32) + if (VT.is64BitVector() && EltSz == 32) return false; return true; @@ -2407,6 +2418,10 @@ static bool isVUZPMask(const SmallVectorImpl<int> &M, EVT VT, static bool isVZIPMask(const SmallVectorImpl<int> &M, EVT VT, unsigned &WhichResult) { + unsigned EltSz = VT.getVectorElementType().getSizeInBits(); + if (EltSz == 64) + return false; + unsigned NumElts = VT.getVectorNumElements(); WhichResult = (M[0] == 0 ? 0 : 1); unsigned Idx = WhichResult * NumElts / 2; @@ -2418,7 +2433,7 @@ static bool isVZIPMask(const SmallVectorImpl<int> &M, EVT VT, } // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32. - if (VT.is64BitVector() && VT.getVectorElementType().getSizeInBits() == 32) + if (VT.is64BitVector() && EltSz == 32) return false; return true; |
