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authorSimon Pilgrim <llvm-dev@redking.me.uk>2018-12-18 09:11:34 +0000
committerSimon Pilgrim <llvm-dev@redking.me.uk>2018-12-18 09:11:34 +0000
commit8488a44c34c7a5bd34ca37765563a2ea1d276f88 (patch)
tree51ee5a3ce63006390c4402d3c2d5a37ecd69cb96
parent784539458fa837ba25aadcb2a99c1323903b694e (diff)
downloadbcm5719-llvm-8488a44c34c7a5bd34ca37765563a2ea1d276f88.tar.gz
bcm5719-llvm-8488a44c34c7a5bd34ca37765563a2ea1d276f88.zip
[X86][SSE] Move VSRAI sign extend in reg fold into SimplifyDemandedBits
(VSRAI (VSHLI X, C1), C1) --> X iff NumSignBits(X) > C1 This works better as part of SimplifyDemandedBits than part of the general combine. llvm-svn: 349462
-rw-r--r--llvm/lib/Target/X86/X86ISelLowering.cpp22
1 files changed, 11 insertions, 11 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 0988fa9dfe3..a6bb174f690 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -32447,12 +32447,21 @@ bool X86TargetLowering::SimplifyDemandedBitsForTargetNode(
if (ShiftImm->getAPIntValue().uge(BitWidth))
break;
+ unsigned ShAmt = ShiftImm->getZExtValue();
+ APInt DemandedMask = OriginalDemandedBits << ShAmt;
+
// If we just want the sign bit then we don't need to shift it.
if (OriginalDemandedBits.isSignMask())
return TLO.CombineTo(Op, Op0);
- unsigned ShAmt = ShiftImm->getZExtValue();
- APInt DemandedMask = OriginalDemandedBits << ShAmt;
+ // fold (VSRAI (VSHLI X, C1), C1) --> X iff NumSignBits(X) > C1
+ if (Op0.getOpcode() == X86ISD::VSHLI && Op1 == Op0.getOperand(1)) {
+ SDValue Op00 = Op0.getOperand(0);
+ unsigned NumSignBits =
+ TLO.DAG.ComputeNumSignBits(Op00, OriginalDemandedElts);
+ if (ShAmt < NumSignBits)
+ return TLO.CombineTo(Op, Op00);
+ }
// If any of the demanded bits are produced by the sign extension, we also
// demand the input sign bit.
@@ -35566,15 +35575,6 @@ static SDValue combineVectorShiftImm(SDNode *N, SelectionDAG &DAG,
if (ISD::isBuildVectorAllZeros(N0.getNode()))
return DAG.getConstant(0, SDLoc(N), VT);
- // fold (VSRAI (VSHLI X, C1), C1) --> X iff NumSignBits(X) > C1
- if (Opcode == X86ISD::VSRAI && N0.getOpcode() == X86ISD::VSHLI &&
- N1 == N0.getOperand(1)) {
- SDValue N00 = N0.getOperand(0);
- unsigned NumSignBits = DAG.ComputeNumSignBits(N00);
- if (ShiftVal < NumSignBits)
- return N00;
- }
-
// Fold (VSRAI (VSRAI X, C1), C2) --> (VSRAI X, (C1 + C2)) with (C1 + C2)
// clamped to (NumBitsPerElt - 1).
if (Opcode == X86ISD::VSRAI && N0.getOpcode() == X86ISD::VSRAI) {
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