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| author | Igor Breger <igor.breger@intel.com> | 2016-05-26 12:42:25 +0000 |
|---|---|---|
| committer | Igor Breger <igor.breger@intel.com> | 2016-05-26 12:42:25 +0000 |
| commit | 8437bb70fdc582b64e3fb0a02033684a2ae386bc (patch) | |
| tree | e2e5994f1918bc095ace9c2b3c7e99903068bfb5 | |
| parent | dc6e951860183131dfc24b8392269eed31924aeb (diff) | |
| download | bcm5719-llvm-8437bb70fdc582b64e3fb0a02033684a2ae386bc.tar.gz bcm5719-llvm-8437bb70fdc582b64e3fb0a02033684a2ae386bc.zip | |
[AVX512] Fix intrinsic cmp{sd|ss} lowering.
Differential Revision: http://reviews.llvm.org/D20615
llvm-svn: 270843
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/avx512-intrinsics.ll | 24 |
2 files changed, 12 insertions, 16 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 680cdd109de..b97303bf584 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -17455,9 +17455,7 @@ static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget &Subtarget MVT::i1), Subtarget, DAG); - return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::i8, - DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i8, CmpMask), - DAG.getValueType(MVT::i1)); + return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, CmpMask); } case COMI: { // Comparison intrinsics ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1; diff --git a/llvm/test/CodeGen/X86/avx512-intrinsics.ll b/llvm/test/CodeGen/X86/avx512-intrinsics.ll index d18fd987ca4..016eab23519 100644 --- a/llvm/test/CodeGen/X86/avx512-intrinsics.ll +++ b/llvm/test/CodeGen/X86/avx512-intrinsics.ll @@ -5659,8 +5659,7 @@ define i8@test_int_x86_avx512_mask_cmp_sd(<2 x double> %x0, <2 x double> %x1, i8 ; CHECK-NEXT: kmovw %edi, %k1 ; CHECK-NEXT: vcmpnltsd {sae}, %xmm1, %xmm0, %k0 {%k1} ; CHECK-NEXT: kmovw %k0, %eax -; CHECK-NEXT: shlb $7, %al -; CHECK-NEXT: sarb $7, %al +; CHECK-NEXT: andl $1, %eax ; CHECK-NEXT: retq %res4 = call i8 @llvm.x86.avx512.mask.cmp.sd(<2 x double> %x0, <2 x double> %x1, i32 5, i8 %x3, i32 8) @@ -5681,8 +5680,7 @@ define i8@test_int_x86_avx512_mask_cmp_sd_all(<2 x double> %x0, <2 x double> %x1 ; CHECK-NEXT: kandw %k2, %k1, %k1 ; CHECK-NEXT: korw %k1, %k0, %k0 ; CHECK-NEXT: kmovw %k0, %eax -; CHECK-NEXT: shlb $7, %al -; CHECK-NEXT: sarb $7, %al +; CHECK-NEXT: andl $1, %eax ; CHECK-NEXT: retq %res1 = call i8 @llvm.x86.avx512.mask.cmp.sd(<2 x double> %x0, <2 x double> %x1, i32 2, i8 -1, i32 4) @@ -5705,8 +5703,7 @@ define i8@test_int_x86_avx512_mask_cmp_ss(<4 x float> %x0, <4 x float> %x1, i8 % ; CHECK-NEXT: kmovw %edi, %k1 ; CHECK-NEXT: vcmpunordss %xmm1, %xmm0, %k0 {%k1} ; CHECK-NEXT: kmovw %k0, %eax -; CHECK-NEXT: shlb $7, %al -; CHECK-NEXT: sarb $7, %al +; CHECK-NEXT: andl $1, %eax ; CHECK-NEXT: retq %res2 = call i8 @llvm.x86.avx512.mask.cmp.ss(<4 x float> %x0, <4 x float> %x1, i32 3, i8 %x3, i32 4) @@ -5719,15 +5716,16 @@ define i8@test_int_x86_avx512_mask_cmp_ss_all(<4 x float> %x0, <4 x float> %x1, ; CHECK: ## BB#0: ; CHECK-NEXT: vcmpless %xmm1, %xmm0, %k1 ; CHECK-NEXT: vcmpunordss {sae}, %xmm1, %xmm0, %k0 {%k1} -; CHECK-NEXT: vcmpneqss %xmm1, %xmm0, %k1 -; CHECK-NEXT: vcmpnltss {sae}, %xmm1, %xmm0, %k1 {%k1} ; CHECK-NEXT: andl $1, %edi -; CHECK-NEXT: kmovw %edi, %k2 -; CHECK-NEXT: kandw %k2, %k1, %k1 -; CHECK-NEXT: kandw %k1, %k0, %k0 +; CHECK-NEXT: kmovw %edi, %k1 +; CHECK-NEXT: vcmpneqss %xmm1, %xmm0, %k2 {%k1} +; CHECK-NEXT: kmovw %k2, %ecx +; CHECK-NEXT: vcmpnltss {sae}, %xmm1, %xmm0, %k1 {%k1} +; CHECK-NEXT: kmovw %k1, %edx +; CHECK-NEXT: andl $1, %edx ; CHECK-NEXT: kmovw %k0, %eax -; CHECK-NEXT: shlb $7, %al -; CHECK-NEXT: sarb $7, %al +; CHECK-NEXT: andb %cl, %al +; CHECK-NEXT: andb %dl, %al ; CHECK-NEXT: retq %res1 = call i8 @llvm.x86.avx512.mask.cmp.ss(<4 x float> %x0, <4 x float> %x1, i32 2, i8 -1, i32 4) %res2 = call i8 @llvm.x86.avx512.mask.cmp.ss(<4 x float> %x0, <4 x float> %x1, i32 3, i8 -1, i32 8) |
