summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorRafael Espindola <rafael.espindola@gmail.com>2011-05-28 00:13:01 +0000
committerRafael Espindola <rafael.espindola@gmail.com>2011-05-28 00:13:01 +0000
commit836f7db2cc9ee29371963dee1e2980bbf2be9d1a (patch)
treec7757ab36805539cfce9a56782237cf6e41e7d6a
parent1d553a2cc4287220ec816cf1b920d7a69d3e7c9d (diff)
downloadbcm5719-llvm-836f7db2cc9ee29371963dee1e2980bbf2be9d1a.tar.gz
bcm5719-llvm-836f7db2cc9ee29371963dee1e2980bbf2be9d1a.zip
Fix the root cause of the bootstrap failure:
There was no way to check if a given register/mode pair was valid. We now return an error code (-2) instead of asserting. If anyone thinks that an assert at this point is really needed, we can autogen a hasValidDwarfRegNum instead. llvm-svn: 132236
-rw-r--r--llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp2
-rw-r--r--llvm/utils/TableGen/RegisterInfoEmitter.cpp9
2 files changed, 3 insertions, 8 deletions
diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
index 5617a0fa4bd..dee6e532262 100644
--- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
@@ -769,7 +769,7 @@ void AsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc) const {
int Reg = TRI->getDwarfRegNum(MLoc.getReg(), false);
for (const unsigned *SR = TRI->getSuperRegisters(MLoc.getReg());
- *SR && Reg == -1; ++SR) {
+ *SR && Reg < 0; ++SR) {
Reg = TRI->getDwarfRegNum(*SR, false);
// FIXME: Get the bit range this register uses of the superregister
// so that we can produce a DW_OP_bit_piece
diff --git a/llvm/utils/TableGen/RegisterInfoEmitter.cpp b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
index 017a5856467..dc263b11772 100644
--- a/llvm/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
@@ -1010,13 +1010,8 @@ void RegisterInfoEmitter::run(raw_ostream &OS) {
for (DwarfRegNumsMapTy::iterator
I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
int RegNo = I->second[i];
- if (RegNo != -2)
- OS << " case " << getQualifiedName(I->first) << ":\n"
- << " return " << RegNo << ";\n";
- else
- OS << " case " << getQualifiedName(I->first) << ":\n"
- << " assert(0 && \"Invalid register for this mode\");\n"
- << " return -1;\n";
+ OS << " case " << getQualifiedName(I->first) << ":\n"
+ << " return " << RegNo << ";\n";
}
OS << " };\n";
}
OpenPOWER on IntegriCloud