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authorSanjay Patel <spatel@rotateright.com>2019-09-25 15:08:33 +0000
committerSanjay Patel <spatel@rotateright.com>2019-09-25 15:08:33 +0000
commit831a7e7068f78be7108672ca6dc66721000fdf61 (patch)
tree1abede5e93e2811c2b11141b3ba5859a204246eb
parent5c3bc3c930d3993a2c5f581112c18a9eb0ba6838 (diff)
downloadbcm5719-llvm-831a7e7068f78be7108672ca6dc66721000fdf61.tar.gz
bcm5719-llvm-831a7e7068f78be7108672ca6dc66721000fdf61.zip
[DAGCombiner] add one-use restriction to vector transform with cheap extract
We might be able to do better on the example in the test, but in general, we should not scalarize a splatted vector binop if there are other uses of the binop. Otherwise, we can end up with code as we had - a scalar op that is redundant with a vector op. llvm-svn: 372886
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp2
-rw-r--r--llvm/test/CodeGen/X86/scalarize-fp.ll17
2 files changed, 8 insertions, 11 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 2b47407393d..80afbbee1b1 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -18990,7 +18990,7 @@ SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
// build_vector.
if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) {
int SplatIndex = SVN->getSplatIndex();
- if (TLI.isExtractVecEltCheap(VT, SplatIndex) &&
+ if (N0.hasOneUse() && TLI.isExtractVecEltCheap(VT, SplatIndex) &&
TLI.isBinOp(N0.getOpcode()) && N0.getNode()->getNumValues() == 1) {
// splat (vector_bo L, R), Index -->
// splat (scalar_bo (extelt L, Index), (extelt R, Index))
diff --git a/llvm/test/CodeGen/X86/scalarize-fp.ll b/llvm/test/CodeGen/X86/scalarize-fp.ll
index 5c72d4ba3c0..5b98272fdce 100644
--- a/llvm/test/CodeGen/X86/scalarize-fp.ll
+++ b/llvm/test/CodeGen/X86/scalarize-fp.ll
@@ -777,21 +777,18 @@ define <8 x float> @splat0_fdiv_const_op0_v8f32(<8 x float> %vx) {
define <4 x float> @multi_use_binop(<4 x float> %x, <4 x float> %y) {
; SSE-LABEL: multi_use_binop:
; SSE: # %bb.0:
-; SSE-NEXT: movaps %xmm0, %xmm2
-; SSE-NEXT: mulps %xmm1, %xmm2
-; SSE-NEXT: mulss %xmm1, %xmm0
-; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0,0,0]
-; SSE-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm2[0]
+; SSE-NEXT: mulps %xmm1, %xmm0
+; SSE-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
+; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1,2,0]
; SSE-NEXT: addps %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: multi_use_binop:
; AVX: # %bb.0:
-; AVX-NEXT: vmulps %xmm1, %xmm0, %xmm2
-; AVX-NEXT: vmulss %xmm1, %xmm0, %xmm0
-; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,0,0]
-; AVX-NEXT: vmovddup {{.*#+}} xmm1 = xmm2[0,0]
-; AVX-NEXT: vaddps %xmm1, %xmm0, %xmm0
+; AVX-NEXT: vmulps %xmm1, %xmm0, %xmm0
+; AVX-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[0,1,2,0]
+; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
+; AVX-NEXT: vaddps %xmm0, %xmm1, %xmm0
; AVX-NEXT: retq
%mul = fmul <4 x float> %x, %y
%mul0 = shufflevector <4 x float> %mul, <4 x float> undef, <4 x i32> <i32 undef, i32 undef, i32 undef, i32 0>
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