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| author | Craig Topper <craig.topper@intel.com> | 2018-06-14 15:40:30 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-06-14 15:40:30 +0000 |
| commit | 82fa048371041b7587edd8f11b27014c60fa38e0 (patch) | |
| tree | 519f7ad2415ff79cbfc7116d8c8cffc1fad5e6fa | |
| parent | b0742bf30d53c9faaa45ff7e4a5ce787c6b8f09a (diff) | |
| download | bcm5719-llvm-82fa048371041b7587edd8f11b27014c60fa38e0.tar.gz bcm5719-llvm-82fa048371041b7587edd8f11b27014c60fa38e0.zip | |
[X86] Remove '128' from the internal name of some scalar FP instructions to be consistent with other scalar instructions.
llvm-svn: 334727
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrAVX512.td | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index e5e8b5555c6..fc9c05ecf37 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -5466,12 +5466,12 @@ multiclass avx512_fp_scalef_all<bits<8> opc, bits<8> opcScaler, string OpcodeStr defm PDZ : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, sched.ZMM, v8f64_info>, avx512_fp_round_packed<opc, OpcodeStr, OpNode, sched.ZMM, v8f64_info>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>; - defm SSZ128 : avx512_fp_scalef_scalar<opcScaler, OpcodeStr, OpNodeScal, sched.Scl, f32x_info>, - avx512_fp_scalar_round<opcScaler, OpcodeStr##"ss", f32x_info, OpNodeScal, sched.Scl>, - EVEX_4V,EVEX_CD8<32, CD8VT1>; - defm SDZ128 : avx512_fp_scalef_scalar<opcScaler, OpcodeStr, OpNodeScal, sched.Scl, f64x_info>, - avx512_fp_scalar_round<opcScaler, OpcodeStr##"sd", f64x_info, OpNodeScal, sched.Scl>, - EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W; + defm SSZ : avx512_fp_scalef_scalar<opcScaler, OpcodeStr, OpNodeScal, sched.Scl, f32x_info>, + avx512_fp_scalar_round<opcScaler, OpcodeStr##"ss", f32x_info, OpNodeScal, sched.Scl>, + EVEX_4V,EVEX_CD8<32, CD8VT1>; + defm SDZ : avx512_fp_scalef_scalar<opcScaler, OpcodeStr, OpNodeScal, sched.Scl, f64x_info>, + avx512_fp_scalar_round<opcScaler, OpcodeStr##"sd", f64x_info, OpNodeScal, sched.Scl>, + EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W; // Define only if AVX512VL feature is present. let Predicates = [HasVLX] in { @@ -9815,8 +9815,8 @@ multiclass avx512_common_fp_sae_scalar_imm<string OpcodeStr, X86VectorVTInfo _, bits<8> opc, SDNode OpNode, SDNode OpNodeRnd, X86SchedWriteWidths sched, Predicate prd> { let Predicates = [prd] in { - defm Z128 : avx512_fp_scalar_imm<opc, OpcodeStr, OpNode, sched.XMM, _>, - avx512_fp_sae_scalar_imm<opc, OpcodeStr, OpNodeRnd, sched.XMM, _>; + defm Z : avx512_fp_scalar_imm<opc, OpcodeStr, OpNode, sched.XMM, _>, + avx512_fp_sae_scalar_imm<opc, OpcodeStr, OpNodeRnd, sched.XMM, _>; } } |
