[Hexagon] Recognize vcombine in copy propagation

llvm-svn: 277528

2 files changed, 56 insertions, 2 deletions

diff --git a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
index d8babdd6075..5db69ae4555 100644
--- a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
@@ -1568,7 +1568,9 @@ bool CopyGeneration::processBlock(MachineBasicBlock &B,
         continue;
       }
 
-      if (FRC == &Hexagon::DoubleRegsRegClass) {
+      if (FRC == &Hexagon::DoubleRegsRegClass ||
+          FRC == &Hexagon::VecDblRegsRegClass ||
+          FRC == &Hexagon::VecDblRegs128BRegClass) {
         // Try to generate REG_SEQUENCE.
         BitTracker::RegisterRef TL = { R, Hexagon::subreg_loreg };
         BitTracker::RegisterRef TH = { R, Hexagon::subreg_hireg };
@@ -1602,6 +1604,8 @@ bool CopyPropagation::isCopyReg(unsigned Opc) {
     case Hexagon::A2_combinew:
     case Hexagon::A4_combineir:
     case Hexagon::A4_combineri:
+    case Hexagon::V6_vcombine:
+    case Hexagon::V6_vcombine_128B:
       return true;
     default:
       break;
@@ -1639,7 +1643,9 @@ bool CopyPropagation::propagateRegCopy(MachineInstr &MI) {
       }
       break;
     }
-    case Hexagon::A2_combinew: {
+    case Hexagon::A2_combinew:
+    case Hexagon::V6_vcombine:
+    case Hexagon::V6_vcombine_128B: {
       BitTracker::RegisterRef RH = MI.getOperand(1), RL = MI.getOperand(2);
       Changed = HBS::replaceSubWithSub(RD.Reg, Hexagon::subreg_loreg,
                                        RL.Reg, RL.Sub, MRI);
diff --git a/llvm/test/CodeGen/Hexagon/propagate-vcombine.ll b/llvm/test/CodeGen/Hexagon/propagate-vcombine.ll
new file mode 100644
index 00000000000..4948a89b73e
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/propagate-vcombine.ll
@@ -0,0 +1,48 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+@v0 = global <16 x i32> zeroinitializer, align 64
+@v1 = global <16 x i32> zeroinitializer, align 64
+
+; CHECK-LABEL: danny:
+; CHECK-NOT: vcombine
+
+define void @danny() #0 {
+  %t0 = load <16 x i32>, <16 x i32>* @v0, align 64
+  %t1 = load <16 x i32>, <16 x i32>* @v1, align 64
+  %t2 = call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %t0, <16 x i32> %t1)
+  %t3 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %t2)
+  %t4 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %t2)
+  store <16 x i32> %t3, <16 x i32>* @v0, align 64
+  store <16 x i32> %t4, <16 x i32>* @v1, align 64
+  ret void
+}
+
+@w0 = global <32 x i32> zeroinitializer, align 128
+@w1 = global <32 x i32> zeroinitializer, align 128
+
+; CHECK-LABEL: sammy:
+; CHECK-NOT: vcombine
+
+define void @sammy() #1 {
+  %t0 = load <32 x i32>, <32 x i32>* @w0, align 128
+  %t1 = load <32 x i32>, <32 x i32>* @w1, align 128
+  %t2 = call <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32> %t0, <32 x i32> %t1)
+  %t3 = tail call <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32> %t2)
+  %t4 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %t2)
+  store <32 x i32> %t3, <32 x i32>* @w0, align 128
+  store <32 x i32> %t4, <32 x i32>* @w1, align 128
+  ret void
+}
+
+declare <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32>, <16 x i32>) #2
+declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #2
+declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #2
+
+declare <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32>, <32 x i32>) #3
+declare <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32>) #3
+declare <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32>) #3
+
+attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx" }
+attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" }
+attributes #2 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx" }
+attributes #3 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" }