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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-11-15 00:05:42 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-11-15 00:05:42 +0000 |
| commit | 81da114e65cf18b719bc88322365248d2e05918b (patch) | |
| tree | 25afbf985300bd643fd7b8691b92a4394fd9d86e | |
| parent | 972034bda9623c0a8441dae1d374c74137f85171 (diff) | |
| download | bcm5719-llvm-81da114e65cf18b719bc88322365248d2e05918b.tar.gz bcm5719-llvm-81da114e65cf18b719bc88322365248d2e05918b.zip | |
AMDGPU: Set hasExtraSrcRegAllocReq on v_div_scale_*
This doesn't solve any problems I know about, but this should have
more conservative assumptions about the operands'
llvm-svn: 286913
| -rw-r--r-- | llvm/lib/Target/AMDGPU/VOP3Instructions.td | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td index 87a7c4044ab..4f8b680e52f 100644 --- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td +++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td @@ -167,11 +167,13 @@ def V_LDEXP_F64 : VOP3Inst <"v_ldexp_f64", VOP3_Profile<VOP_F64_F64_I32>, AMDGPU def V_DIV_SCALE_F32 : VOP3_Pseudo <"v_div_scale_f32", VOP3b_F32_I1_F32_F32_F32, [], 1> { let SchedRW = [WriteFloatFMA, WriteSALU]; + let hasExtraSrcRegAllocReq = 1; } // Double precision division pre-scale. def V_DIV_SCALE_F64 : VOP3_Pseudo <"v_div_scale_f64", VOP3b_F64_I1_F64_F64_F64, [], 1> { let SchedRW = [WriteDouble, WriteSALU]; + let hasExtraSrcRegAllocReq = 1; } def V_MSAD_U8 : VOP3Inst <"v_msad_u8", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_msad_u8>; |
