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| author | Rafael Espindola <rafael.espindola@gmail.com> | 2013-05-01 13:00:16 +0000 |
|---|---|---|
| committer | Rafael Espindola <rafael.espindola@gmail.com> | 2013-05-01 13:00:16 +0000 |
| commit | 817c1d92b45c246ca032ef0c7b5a58f95b4fea8b (patch) | |
| tree | 97eb960eeb5261a17c2e474a586f7a8192ac0bfa | |
| parent | 59d55219cf02676d28ffa1f44d3a11e96c1dd939 (diff) | |
| download | bcm5719-llvm-817c1d92b45c246ca032ef0c7b5a58f95b4fea8b.tar.gz bcm5719-llvm-817c1d92b45c246ca032ef0c7b5a58f95b4fea8b.zip | |
Put VMOVPQIto64rr in the VRPDI class.
Patch by Joshua Magee.
llvm-svn: 180842
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrSSE.td | 6 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/avx-basic.ll | 10 |
2 files changed, 13 insertions, 3 deletions
diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td index 4d6097faae4..cce938baafe 100644 --- a/llvm/lib/Target/X86/X86InstrSSE.td +++ b/llvm/lib/Target/X86/X86InstrSSE.td @@ -4462,12 +4462,12 @@ def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src), // Move Packed Doubleword Int first element to Doubleword Int // let SchedRW = [WriteMove] in { -def VMOVPQIto64rr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src), - "vmov{d|q}\t{$src, $dst|$dst, $src}", +def VMOVPQIto64rr : VRPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src), + "mov{d|q}\t{$src, $dst|$dst, $src}", [(set GR64:$dst, (vector_extract (v2i64 VR128:$src), (iPTR 0)))], IIC_SSE_MOVD_ToGP>, - TB, OpSize, VEX, VEX_W, Requires<[HasAVX, In64BitMode]>; + VEX; def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src), "mov{d|q}\t{$src, $dst|$dst, $src}", diff --git a/llvm/test/CodeGen/X86/avx-basic.ll b/llvm/test/CodeGen/X86/avx-basic.ll index 95854c7960e..64c4627c47c 100644 --- a/llvm/test/CodeGen/X86/avx-basic.ll +++ b/llvm/test/CodeGen/X86/avx-basic.ll @@ -121,3 +121,13 @@ define <16 x i16> @build_vec_16x16(i16 %a) nounwind readonly { %res = insertelement <16 x i16> <i16 undef, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, i16 %a, i32 0 ret <16 x i16> %res } + +;;; Check that VMOVPQIto64rr generates the assembly string "vmovd". Previously +;;; an incorrect mnemonic of "movd" was printed for this instruction. +; CHECK: VMOVPQIto64rr +; CHECK: vmovd +define i64 @VMOVPQIto64rr(<2 x i64> %a) { +entry: + %vecext.i = extractelement <2 x i64> %a, i32 0 + ret i64 %vecext.i +} |
