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| author | Evandro Menezes <e.menezes@samsung.com> | 2018-10-24 20:03:20 +0000 |
|---|---|---|
| committer | Evandro Menezes <e.menezes@samsung.com> | 2018-10-24 20:03:20 +0000 |
| commit | 80bc136732166bb5bafeef93abeffc50453f3235 (patch) | |
| tree | 565f43ec801ab1da8995305d8d28aac15f78fe19 | |
| parent | cd4deea1c4e84187c109349f5c34fd579932bb60 (diff) | |
| download | bcm5719-llvm-80bc136732166bb5bafeef93abeffc50453f3235.tar.gz bcm5719-llvm-80bc136732166bb5bafeef93abeffc50453f3235.zip | |
[AArch64] Fix overlapping instructions
Fix overlapping instruction descriptions in the machine model for Exynos M3.
Effectively, NFC.
llvm-svn: 345186
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64SchedExynosM3.td | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64SchedExynosM3.td b/llvm/lib/Target/AArch64/AArch64SchedExynosM3.td index 5e5369a5a7f..56808c291b1 100644 --- a/llvm/lib/Target/AArch64/AArch64SchedExynosM3.td +++ b/llvm/lib/Target/AArch64/AArch64SchedExynosM3.td @@ -26,9 +26,6 @@ def ExynosM3Model : SchedMachineModel { let CompleteModel = 1; // Use the default model otherwise. list<Predicate> UnsupportedFeatures = [HasSVE]; - - // FIXME: Remove when all errors have been fixed. - let FullInstRWOverlapCheck = 0; } //===----------------------------------------------------------------------===// @@ -588,7 +585,7 @@ def : InstRW<[M3WriteSA, // ASIMD instructions. def : InstRW<[M3WriteNMSC3], (instregex "^[SU]ABAL?v")>; def : InstRW<[M3WriteNMSC1], (instregex "^[SU]ABDL?v")>; -def : InstRW<[M3WriteNMSC1], (instregex "^(SQ)?(ABS|NEG)v")>; +def : InstRW<[M3WriteNMSC1], (instregex "^((SQ)?ABS|SQNEG)v")>; def : InstRW<[M3WriteNALU1], (instregex "^(ADD|NEG|SUB)v")>; def : InstRW<[M3WriteNMSC3], (instregex "^[SU]?ADDL?Pv")>; def : InstRW<[M3WriteNMSC3], (instregex "^[SU]H(ADD|SUB)v")>; @@ -597,7 +594,6 @@ def : InstRW<[M3WriteNMSC3], (instregex "^R?(ADD|SUB)HN2?v")>; def : InstRW<[M3WriteNMSC3], (instregex "^[SU]Q(ADD|SUB)v")>; def : InstRW<[M3WriteNMSC3], (instregex "^(SU|US)QADDv")>; def : InstRW<[M3WriteNMSC3], (instregex "^[SU]RHADDv")>; -def : InstRW<[M3WriteNMSC3], (instregex "^[SU]?ADDL?Vv")>; def : InstRW<[M3WriteNMSC1], (instregex "^CM(EQ|GE|GT|HI|HS|LE|LT)v")>; def : InstRW<[M3WriteNALU1], (instregex "^CMTSTv")>; def : InstRW<[M3WriteNALU1], (instregex "^(AND|BIC|EOR|MVNI|NOT|ORN|ORR)v")>; |
