diff options
| author | Sanjay Patel <spatel@rotateright.com> | 2015-11-22 00:03:16 +0000 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2015-11-22 00:03:16 +0000 |
| commit | 8066d906f179ba417e16a89f51f1a9196550966e (patch) | |
| tree | 2ff1f7834c338df38a66738d94da84efc73a898e | |
| parent | b37c4c414b04ce9467ed21d9a4649a8c47ab3e3c (diff) | |
| download | bcm5719-llvm-8066d906f179ba417e16a89f51f1a9196550966e.tar.gz bcm5719-llvm-8066d906f179ba417e16a89f51f1a9196550966e.zip | |
fix formatting; NFC
llvm-svn: 253802
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 219f1864229..97a1d6c72c2 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -6337,7 +6337,7 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const { // One half is zero or undef. unsigned Idx = countTrailingZeros(NonZeros); SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, - Op.getOperand(Idx)); + Op.getOperand(Idx)); return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG); } return SDValue(); @@ -6345,13 +6345,13 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const { // If element VT is < 32 bits, convert it to inserts into a zero vector. if (EVTBits == 8 && NumElems == 16) - if (SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG, - Subtarget, *this)) + if (SDValue V = LowerBuildVectorv16i8(Op, NonZeros, NumNonZero, NumZero, + DAG, Subtarget, *this)) return V; if (EVTBits == 16 && NumElems == 8) - if (SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG, - Subtarget, *this)) + if (SDValue V = LowerBuildVectorv8i16(Op, NonZeros, NumNonZero, NumZero, + DAG, Subtarget, *this)) return V; // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS |
