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author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-05-17 11:49:35 +0000 |
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committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-05-17 11:49:35 +0000 |
commit | 7f8ea15ffa193e0c5b8d0b20df335754ef038bcc (patch) | |
tree | 8b498e647ec0e7b4b2e2fa24761a65795414d0ee | |
parent | 6ff6a8f656eeb59f2051568334b82e1615bdca48 (diff) | |
download | bcm5719-llvm-7f8ea15ffa193e0c5b8d0b20df335754ef038bcc.tar.gz bcm5719-llvm-7f8ea15ffa193e0c5b8d0b20df335754ef038bcc.zip |
GlobalISel: Add MIRBuilder wrappers for bitcount instructions
Various expansions use these.
llvm-svn: 361018
-rw-r--r-- | llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h | 25 | ||||
-rw-r--r-- | llvm/unittests/CodeGen/GlobalISel/MachineIRBuilderTest.cpp | 27 |
2 files changed, 52 insertions, 0 deletions
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h index f48843441ff..e45a07d231b 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h @@ -1256,6 +1256,31 @@ public: return buildInstr(TargetOpcode::G_XOR, {Dst}, {Src0, NegOne}); } + /// Build and insert \p Res = G_CTPOP \p Op0, \p Src0 + MachineInstrBuilder buildCTPOP(const DstOp &Dst, const SrcOp &Src0) { + return buildInstr(TargetOpcode::G_CTPOP, {Dst}, {Src0}); + } + + /// Build and insert \p Res = G_CTLZ \p Op0, \p Src0 + MachineInstrBuilder buildCTLZ(const DstOp &Dst, const SrcOp &Src0) { + return buildInstr(TargetOpcode::G_CTLZ, {Dst}, {Src0}); + } + + /// Build and insert \p Res = G_CTLZ_ZERO_UNDEF \p Op0, \p Src0 + MachineInstrBuilder buildCTLZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0) { + return buildInstr(TargetOpcode::G_CTLZ_ZERO_UNDEF, {Dst}, {Src0}); + } + + /// Build and insert \p Res = G_CTTZ \p Op0, \p Src0 + MachineInstrBuilder buildCTTZ(const DstOp &Dst, const SrcOp &Src0) { + return buildInstr(TargetOpcode::G_CTTZ, {Dst}, {Src0}); + } + + /// Build and insert \p Res = G_CTTZ_ZERO_UNDEF \p Op0, \p Src0 + MachineInstrBuilder buildCTTZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0) { + return buildInstr(TargetOpcode::G_CTTZ_ZERO_UNDEF, {Dst}, {Src0}); + } + /// Build and insert \p Res = G_FADD \p Op0, \p Op1 MachineInstrBuilder buildFAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1) { diff --git a/llvm/unittests/CodeGen/GlobalISel/MachineIRBuilderTest.cpp b/llvm/unittests/CodeGen/GlobalISel/MachineIRBuilderTest.cpp index aec6d46b3c0..c696620958d 100644 --- a/llvm/unittests/CodeGen/GlobalISel/MachineIRBuilderTest.cpp +++ b/llvm/unittests/CodeGen/GlobalISel/MachineIRBuilderTest.cpp @@ -202,3 +202,30 @@ TEST_F(GISelMITest, BuildXor) { EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF; } + +TEST_F(GISelMITest, BuildBitCounts) { + if (!TM) + return; + + LLT S32 = LLT::scalar(32); + SmallVector<unsigned, 4> Copies; + collectCopies(Copies, MF); + + B.buildCTPOP(S32, Copies[0]); + B.buildCTLZ(S32, Copies[0]); + B.buildCTLZ_ZERO_UNDEF(S32, Copies[1]); + B.buildCTTZ(S32, Copies[0]); + B.buildCTTZ_ZERO_UNDEF(S32, Copies[1]); + + auto CheckStr = R"( + ; CHECK: [[COPY0:%[0-9]+]]:_(s64) = COPY $x0 + ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1 + ; CHECK: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[COPY0]]:_ + ; CHECK: [[CTLZ0:%[0-9]+]]:_(s32) = G_CTLZ [[COPY0]]:_ + ; CHECK: [[CTLZ_UNDEF0:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[COPY1]]:_ + ; CHECK: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[COPY0]]:_ + ; CHECK: [[CTTZ_UNDEF0:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[COPY1]]:_ + )"; + + EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF; +} |