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| author | Adam Nemet <anemet@apple.com> | 2014-08-07 23:53:38 +0000 |
|---|---|---|
| committer | Adam Nemet <anemet@apple.com> | 2014-08-07 23:53:38 +0000 |
| commit | 7d498629f1e038d2642116b40a04f4acf6532a26 (patch) | |
| tree | 931d788bb095c5a753ad94203eeb54e55b8bc165 | |
| parent | cdc029d04b4122a1503072c5a56fe33f6191d806 (diff) | |
| download | bcm5719-llvm-7d498629f1e038d2642116b40a04f4acf6532a26.tar.gz bcm5719-llvm-7d498629f1e038d2642116b40a04f4acf6532a26.zip | |
[AVX512] Add zero-masking variant to AVX512_masking multiclass
This completes one item from the todo-list of r215125 "Generate masking
instruction variants with tablegen".
The AddedComplexity is needed just like for the k variant.
Added a codegen test based on valignq.
llvm-svn: 215173
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrAVX512.td | 14 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/avx512-shuffle.ll | 9 |
2 files changed, 21 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index a62e926629e..eaf52536c5a 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -1,7 +1,7 @@ multiclass AVX512_masking<bits<8> O, Format F, dag Outs, dag Ins, string OpcodeStr, string AttSrcAsm, string IntelSrcAsm, - dag RHS, + dag RHS, ValueType OpVT, RegisterClass RC, RegisterClass KRC> { def NAME: AVX512<O, F, Outs, Ins, OpcodeStr#" \t{"#AttSrcAsm#", $dst|"# @@ -17,6 +17,16 @@ multiclass AVX512_masking<bits<8> O, Format F, dag Outs, dag Ins, [(set RC:$dst, (vselect KRC:$mask, RHS, RC:$src0))]>, EVEX_K; + let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<> + def NAME#kz: AVX512<O, F, Outs, + !con((ins KRC:$mask), Ins), + OpcodeStr#" \t{"#AttSrcAsm#", $dst {${mask}} {z}|"# + "$dst {${mask}} {z}, "#IntelSrcAsm#"}", + [(set RC:$dst, + (vselect KRC:$mask, RHS, + (OpVT (bitconvert + (v16i32 immAllZerosV)))))]>, + EVEX_KZ; } // Bitcasts between 512-bit vector types. Return the original type since @@ -4491,7 +4501,7 @@ multiclass avx512_valign<string Suffix, RegisterClass RC, RegisterClass KRC, "$src3, $src2, $src1", "$src1, $src2, $src3", (IntVT (X86VAlign RC:$src2, RC:$src1, (i8 imm:$src3))), - RC, KRC>, + IntVT, RC, KRC>, AVX512AIi8Base, EVEX_4V; // Also match valign of packed floats. diff --git a/llvm/test/CodeGen/X86/avx512-shuffle.ll b/llvm/test/CodeGen/X86/avx512-shuffle.ll index a4aa87a2ea9..bae99d97b21 100644 --- a/llvm/test/CodeGen/X86/avx512-shuffle.ll +++ b/llvm/test/CodeGen/X86/avx512-shuffle.ll @@ -216,6 +216,15 @@ define <8 x i64> @test16k(<8 x i64> %a, <8 x i64> %b, <8 x i64> %src, i8 %mask) ret <8 x i64> %res } +; CHECK-LABEL: test16kz +; CHECK: valignq $2, %zmm0, %zmm1, %zmm0 {%k1} {z} ## encoding: [0x62,0xf3,0xf5,0xc9,0x03,0xc0,0x02] +define <8 x i64> @test16kz(<8 x i64> %a, <8 x i64> %b, i8 %mask) nounwind { + %c = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9> + %m = bitcast i8 %mask to <8 x i1> + %res = select <8 x i1> %m, <8 x i64> %c, <8 x i64> zeroinitializer + ret <8 x i64> %res +} + ; CHECK-LABEL: test17 ; CHECK: vshufpd $19, %zmm1, %zmm0 ; CHECK: ret |
