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| author | Justin Holewinski <jholewinski@nvidia.com> | 2013-06-21 18:51:24 +0000 |
|---|---|---|
| committer | Justin Holewinski <jholewinski@nvidia.com> | 2013-06-21 18:51:24 +0000 |
| commit | 7ceab3a892b763aa8dae2c998ab7fad4badfafc9 (patch) | |
| tree | aae1d54f6ee4ebc5c41b154b11a47b047b79de36 | |
| parent | d8576e19cebd206a30649e17be695f1557332706 (diff) | |
| download | bcm5719-llvm-7ceab3a892b763aa8dae2c998ab7fad4badfafc9.tar.gz bcm5719-llvm-7ceab3a892b763aa8dae2c998ab7fad4badfafc9.zip | |
[NVPTX] Add NVPTX register constraints
llvm-svn: 184578
| -rw-r--r-- | clang/lib/Basic/Targets.cpp | 15 | ||||
| -rw-r--r-- | clang/test/CodeGen/nvptx-inlineasm-ptx.c | 40 |
2 files changed, 52 insertions, 3 deletions
diff --git a/clang/lib/Basic/Targets.cpp b/clang/lib/Basic/Targets.cpp index 744a437fde5..737dd873b62 100644 --- a/clang/lib/Basic/Targets.cpp +++ b/clang/lib/Basic/Targets.cpp @@ -1290,9 +1290,18 @@ namespace { NumAliases = 0; } virtual bool validateAsmConstraint(const char *&Name, - TargetInfo::ConstraintInfo &info) const { - // FIXME: implement - return true; + TargetInfo::ConstraintInfo &Info) const { + switch (*Name) { + default: return false; + case 'c': + case 'h': + case 'r': + case 'l': + case 'f': + case 'd': + Info.setAllowsRegister(); + return true; + } } virtual const char *getClobbers() const { // FIXME: Is this really right? diff --git a/clang/test/CodeGen/nvptx-inlineasm-ptx.c b/clang/test/CodeGen/nvptx-inlineasm-ptx.c new file mode 100644 index 00000000000..8432e6c271d --- /dev/null +++ b/clang/test/CodeGen/nvptx-inlineasm-ptx.c @@ -0,0 +1,40 @@ +// RUN: %clang_cc1 -triple nvptx-unknown-unknown -O3 -S -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple nvptx64-unknown-unknown -O3 -S -o - %s | FileCheck %s + +void constraints() { + char c; + unsigned char uc; + short s; + unsigned short us; + int i; + unsigned int ui; + long l; + unsigned long ul; + float f; + double d; + + // CHECK: mov.b8 %rc{{[0-9]+}}, %rc{{[0-9]+}} + asm volatile ("mov.b8 %0, %1;" : "=c"(c) : "c"(c)); + // CHECK: mov.b8 %rc{{[0-9]+}}, %rc{{[0-9]+}} + asm volatile ("mov.b8 %0, %1;" : "=c"(uc) : "c"(uc)); + + // CHECK: mov.b16 %rs{{[0-9]+}}, %rs{{[0-9]+}} + asm volatile ("mov.b16 %0, %1;" : "=h"(s) : "h"(s)); + // CHECK: mov.b16 %rs{{[0-9]+}}, %rs{{[0-9]+}} + asm volatile ("mov.b16 %0, %1;" : "=h"(us) : "h"(us)); + + // CHECK: mov.b32 %r{{[0-9]+}}, %r{{[0-9]+}} + asm volatile ("mov.b32 %0, %1;" : "=r"(i) : "r"(i)); + // CHECK: mov.b32 %r{{[0-9]+}}, %r{{[0-9]+}} + asm volatile ("mov.b32 %0, %1;" : "=r"(ui) : "r"(ui)); + + // CHECK: mov.b64 %rl{{[0-9]+}}, %rl{{[0-9]+}} + asm volatile ("mov.b64 %0, %1;" : "=l"(l) : "l"(l)); + // CHECK: mov.b64 %rl{{[0-9]+}}, %rl{{[0-9]+}} + asm volatile ("mov.b64 %0, %1;" : "=l"(ul) : "l"(ul)); + + // CHECK: mov.b32 %f{{[0-9]+}}, %f{{[0-9]+}} + asm volatile ("mov.b32 %0, %1;" : "=f"(f) : "f"(f)); + // CHECK: mov.b64 %fl{{[0-9]+}}, %fl{{[0-9]+}} + asm volatile ("mov.b64 %0, %1;" : "=d"(d) : "d"(d)); +} |
