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authorCameron McInally <cameron.mcinally@nyu.edu>2019-05-14 16:51:18 +0000
committerCameron McInally <cameron.mcinally@nyu.edu>2019-05-14 16:51:18 +0000
commit7c5c0c9fe59b77e628024dec48b9db1f36f41c15 (patch)
tree69888b3eb2d2b8422e08baab1e599da61174cff7
parent19ae9d010dcfaa14b86fdcdeae14b7bebf1a281b (diff)
downloadbcm5719-llvm-7c5c0c9fe59b77e628024dec48b9db1f36f41c15.tar.gz
bcm5719-llvm-7c5c0c9fe59b77e628024dec48b9db1f36f41c15.zip
Support FNeg in SpeculativeExecution pass
Differential Revision: https://reviews.llvm.org/D61910 llvm-svn: 360692
-rw-r--r--llvm/lib/Transforms/Scalar/SpeculativeExecution.cpp1
-rw-r--r--llvm/test/Transforms/SpeculativeExecution/spec-fp.ll18
2 files changed, 17 insertions, 2 deletions
diff --git a/llvm/lib/Transforms/Scalar/SpeculativeExecution.cpp b/llvm/lib/Transforms/Scalar/SpeculativeExecution.cpp
index 79d2a52b393..f9d027eb4a3 100644
--- a/llvm/lib/Transforms/Scalar/SpeculativeExecution.cpp
+++ b/llvm/lib/Transforms/Scalar/SpeculativeExecution.cpp
@@ -240,6 +240,7 @@ static unsigned ComputeSpeculationCost(const Instruction *I,
case Instruction::FMul:
case Instruction::FDiv:
case Instruction::FRem:
+ case Instruction::FNeg:
case Instruction::ICmp:
case Instruction::FCmp:
return TTI.getUserCost(I);
diff --git a/llvm/test/Transforms/SpeculativeExecution/spec-fp.ll b/llvm/test/Transforms/SpeculativeExecution/spec-fp.ll
index efab8ab704c..181ce3757d4 100644
--- a/llvm/test/Transforms/SpeculativeExecution/spec-fp.ll
+++ b/llvm/test/Transforms/SpeculativeExecution/spec-fp.ll
@@ -30,10 +30,10 @@ b:
ret void
}
-; CHECK-LABEL: @ifThen_fneg(
+; CHECK-LABEL: @ifThen_binary_fneg(
; CHECK: fsub float -0.0
; CHECK: br i1 true
-define void @ifThen_fneg() {
+define void @ifThen_binary_fneg() {
br i1 true, label %a, label %b
a:
@@ -44,6 +44,20 @@ b:
ret void
}
+; CHECK-LABEL: @ifThen_unary_fneg(
+; CHECK: fneg float
+; CHECK: br i1 true
+define void @ifThen_unary_fneg() {
+ br i1 true, label %a, label %b
+
+a:
+ %x = fneg float undef
+ br label %b
+
+b:
+ ret void
+}
+
; CHECK-LABEL: @ifThen_fmul(
; CHECK: fmul
; CHECK: br i1 true
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