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| author | Andrew Lenharth <andrewl@lenharth.org> | 2005-12-01 17:48:51 +0000 |
|---|---|---|
| committer | Andrew Lenharth <andrewl@lenharth.org> | 2005-12-01 17:48:51 +0000 |
| commit | 7bb09912c845e2130be2a65b835bf1ce22bc18fd (patch) | |
| tree | 27a6912811693bc1904e6258cc25a7a705afd83b | |
| parent | 006bb04f3ab11fabf0d7f01149ce687fb508125a (diff) | |
| download | bcm5719-llvm-7bb09912c845e2130be2a65b835bf1ce22bc18fd.tar.gz bcm5719-llvm-7bb09912c845e2130be2a65b835bf1ce22bc18fd.zip | |
major think-o
llvm-svn: 24564
| -rw-r--r-- | llvm/lib/Target/Alpha/AlphaISelPattern.cpp | 15 |
1 files changed, 10 insertions, 5 deletions
diff --git a/llvm/lib/Target/Alpha/AlphaISelPattern.cpp b/llvm/lib/Target/Alpha/AlphaISelPattern.cpp index 5423393be7d..44b38282f01 100644 --- a/llvm/lib/Target/Alpha/AlphaISelPattern.cpp +++ b/llvm/lib/Target/Alpha/AlphaISelPattern.cpp @@ -1538,23 +1538,28 @@ unsigned AlphaISel::SelectExpr(SDOperand N) { return Result; case AlphaISD::CVTQT_: - BuildMI(BB, Alpha::CVTQT, 1, Result).addReg(SelectExpr(N.getOperand(0))); + Tmp1 = SelectExpr(N.getOperand(0)); + BuildMI(BB, Alpha::CVTQT, 1, Result).addReg(Tmp1); return Result; case AlphaISD::CVTQS_: - BuildMI(BB, Alpha::CVTQS, 1, Result).addReg(SelectExpr(N.getOperand(0))); + Tmp1 = SelectExpr(N.getOperand(0)); + BuildMI(BB, Alpha::CVTQS, 1, Result).addReg(Tmp1); return Result; case AlphaISD::CVTTQ_: - BuildMI(BB, Alpha::CVTTQ, 1, Result).addReg(SelectExpr(N.getOperand(0))); + Tmp1 = SelectExpr(N.getOperand(0)); + BuildMI(BB, Alpha::CVTTQ, 1, Result).addReg(Tmp1); return Result; case AlphaISD::ITOFT_: - BuildMI(BB, Alpha::ITOFT, 1, Result).addReg(SelectExpr(N.getOperand(0))); + Tmp1 = SelectExpr(N.getOperand(0)); + BuildMI(BB, Alpha::ITOFT, 1, Result).addReg(Tmp1); return Result; case AlphaISD::FTOIT_: - BuildMI(BB, Alpha::FTOIT, 1, Result).addReg(SelectExpr(N.getOperand(0))); + Tmp1 = SelectExpr(N.getOperand(0)); + BuildMI(BB, Alpha::FTOIT, 1, Result).addReg(Tmp1); return Result; case ISD::AssertSext: |
