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| author | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2016-09-16 15:12:43 +0000 |
|---|---|---|
| committer | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2016-09-16 15:12:43 +0000 |
| commit | 7b3b2e7f652d17ceea538d03da1db3c3fc379e22 (patch) | |
| tree | 22e1b5bfe37584d4206a60f638c09bff3d2a0e9c | |
| parent | 90637f61961bd7a3d2c56b15ced60b36ca6ca940 (diff) | |
| download | bcm5719-llvm-7b3b2e7f652d17ceea538d03da1db3c3fc379e22.tar.gz bcm5719-llvm-7b3b2e7f652d17ceea538d03da1db3c3fc379e22.zip | |
[AArch64][GlobalISel] Add default regbank mapping for G_FCMP.
llvm-svn: 281738
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp | 10 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir | 21 |
2 files changed, 31 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp b/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp index ab70820e086..dab6225e4cf 100644 --- a/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp @@ -221,6 +221,16 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { OpBanks[Idx] = AArch64::GPRRegBankID; } + // Some of the floating-point instructions have mixed GPR and FPR operands: + // fine-tune the computed mapping. + switch (Opc) { + case TargetOpcode::G_FCMP: { + OpBanks = {AArch64::GPRRegBankID, /* Predicate */ 0, AArch64::FPRRegBankID, + AArch64::FPRRegBankID}; + break; + } + } + // Finally construct the computed mapping. for (unsigned Idx = 0; Idx < MI.getNumOperands(); ++Idx) if (MI.getOperand(Idx).isReg()) diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir index c8cf12343c6..740223d5468 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir @@ -59,6 +59,8 @@ define void @test_fconstant_s32() { ret void } + define void @test_fcmp_s32() { ret void } + ... --- @@ -766,3 +768,22 @@ body: | ; CHECK: %0(s32) = G_FCONSTANT float 1.0 %0(s32) = G_FCONSTANT float 1.0 ... + +--- +# CHECK-LABEL: name: test_fcmp_s32 +name: test_fcmp_s32 +legalized: true +# CHECK: registers: +# CHECK: - { id: 0, class: fpr } +# CHECK: - { id: 1, class: gpr } +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } +body: | + bb.0: + liveins: %s0 + ; CHECK: %0(s32) = COPY %s0 + ; CHECK: %1(s1) = G_FCMP floatpred(olt), %0(s32), %0 + %0(s32) = COPY %s0 + %1(s1) = G_FCMP floatpred(olt), %0, %0 +... |
