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authorHans Wennborg <hans@hanshq.net>2018-08-16 09:58:56 +0000
committerHans Wennborg <hans@hanshq.net>2018-08-16 09:58:56 +0000
commit7b0a6d324692b5861e001f943e84dbb6187c6926 (patch)
treec022ba7e6ff5d41647eca594e26ee322c4edbaab
parent9dc31a87e7e8d872023f9c65feaeee201b27c927 (diff)
downloadbcm5719-llvm-7b0a6d324692b5861e001f943e84dbb6187c6926.tar.gz
bcm5719-llvm-7b0a6d324692b5861e001f943e84dbb6187c6926.zip
Merging r339533:
------------------------------------------------------------------------ r339533 | ctopper | 2018-08-13 07:26:49 +0200 (Mon, 13 Aug 2018) | 5 lines [SelectionDAG] In PromoteFloatRes_BITCAST, insert a bitcast before the fp16_to_fp in case the input type isn't an i16. The bitcast can be further legalized as needed. Fixes PR38533. ------------------------------------------------------------------------ llvm-svn: 339855
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp6
-rw-r--r--llvm/test/CodeGen/X86/pr38533.ll11
2 files changed, 15 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
index 9aa0ea15f3b..feca1c10f52 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
@@ -1941,8 +1941,10 @@ void DAGTypeLegalizer::PromoteFloatResult(SDNode *N, unsigned ResNo) {
SDValue DAGTypeLegalizer::PromoteFloatRes_BITCAST(SDNode *N) {
EVT VT = N->getValueType(0);
EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
- return DAG.getNode(GetPromotionOpcode(VT, NVT), SDLoc(N), NVT,
- N->getOperand(0));
+ // Input type isn't guaranteed to be i16 so bitcast if not. The bitcast
+ // will be legalized further if necessary.
+ SDValue Cast = DAG.getBitcast(MVT::i16, N->getOperand(0));
+ return DAG.getNode(GetPromotionOpcode(VT, NVT), SDLoc(N), NVT, Cast);
}
SDValue DAGTypeLegalizer::PromoteFloatRes_ConstantFP(SDNode *N) {
diff --git a/llvm/test/CodeGen/X86/pr38533.ll b/llvm/test/CodeGen/X86/pr38533.ll
new file mode 100644
index 00000000000..4c57d84fe65
--- /dev/null
+++ b/llvm/test/CodeGen/X86/pr38533.ll
@@ -0,0 +1,11 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s
+
+define void @constant_fold_vector_to_half() {
+; CHECK-LABEL: constant_fold_vector_to_half:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movw $16384, (%rax) # imm = 0x4000
+; CHECK-NEXT: retq
+ store volatile half bitcast (<4 x i4> <i4 0, i4 0, i4 0, i4 4> to half), half* undef
+ ret void
+}
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