[AArch64][SVE] Add patterns for scalable vselect

This patch matches scalable vector selects to predicated move instructions.

Differential Revision: https://reviews.llvm.org/D71298

3 files changed, 97 insertions, 2 deletions

diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index a531b8a1790..350aa63a263 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -231,7 +231,7 @@ let Predicates = [HasSVE] in {
   defm CPY_ZPmV : sve_int_perm_cpy_v<"cpy">;
 
   // Select elements from either vector (predicated)
-  defm SEL_ZPZZ    : sve_int_sel_vvv<"sel">;
+  defm SEL_ZPZZ    : sve_int_sel_vvv<"sel", vselect>;
 
   defm SPLICE_ZPZ : sve_int_perm_splice<"splice">;
   defm COMPACT_ZPZ : sve_int_perm_compact<"compact">;
diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td
index 2d3a56ee5f7..4be57550df3 100644
--- a/llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -1027,12 +1027,22 @@ class sve_int_sel_vvv<bits<2> sz8_64, string asm, ZPRRegOp zprty>
   let Inst{4-0}   = Zd;
 }
 
-multiclass sve_int_sel_vvv<string asm> {
+multiclass sve_int_sel_vvv<string asm, SDPatternOperator op> {
   def _B : sve_int_sel_vvv<0b00, asm, ZPR8>;
   def _H : sve_int_sel_vvv<0b01, asm, ZPR16>;
   def _S : sve_int_sel_vvv<0b10, asm, ZPR32>;
   def _D : sve_int_sel_vvv<0b11, asm, ZPR64>;
 
+  def : SVE_3_Op_Pat<nxv16i8, op, nxv16i1, nxv16i8, nxv16i8, !cast<Instruction>(NAME # _B)>;
+  def : SVE_3_Op_Pat<nxv8i16, op, nxv8i1,  nxv8i16, nxv8i16, !cast<Instruction>(NAME # _H)>;
+  def : SVE_3_Op_Pat<nxv4i32, op, nxv4i1,  nxv4i32, nxv4i32, !cast<Instruction>(NAME # _S)>;
+  def : SVE_3_Op_Pat<nxv2i64, op, nxv2i1,  nxv2i64, nxv2i64, !cast<Instruction>(NAME # _D)>;
+
+  def : SVE_3_Op_Pat<nxv8f16, op, nxv8i1,  nxv8f16, nxv8f16, !cast<Instruction>(NAME # _H)>;
+  def : SVE_3_Op_Pat<nxv4f32, op, nxv4i1,  nxv4f32, nxv4f32, !cast<Instruction>(NAME # _S)>;
+  def : SVE_3_Op_Pat<nxv2f32, op, nxv2i1,  nxv2f32, nxv2f32, !cast<Instruction>(NAME # _D)>;
+  def : SVE_3_Op_Pat<nxv2f64, op, nxv2i1,  nxv2f64, nxv2f64, !cast<Instruction>(NAME # _D)>;
+
   def : InstAlias<"mov $Zd, $Pg/m, $Zn",
                   (!cast<Instruction>(NAME # _B) ZPR8:$Zd, PPRAny:$Pg, ZPR8:$Zn, ZPR8:$Zd), 1>;
   def : InstAlias<"mov $Zd, $Pg/m, $Zn",
diff --git a/llvm/test/CodeGen/AArch64/sve-select.ll b/llvm/test/CodeGen/AArch64/sve-select.ll
new file mode 100644
index 00000000000..2d2ea47ae35
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/sve-select.ll
@@ -0,0 +1,85 @@
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
+
+; Integer vector select
+
+define <vscale x 16 x i8> @sel_nxv16i8(<vscale x 16 x i1> %p,
+                                       <vscale x 16 x i8> %dst,
+                                       <vscale x 16 x i8> %a) {
+; CHECK-LABEL: sel_nxv16i8:
+; CHECK:         mov z0.b, p0/m, z1.b
+; CHECK-NEXT:    ret
+  %sel = select <vscale x 16 x i1> %p, <vscale x 16 x i8> %a, <vscale x 16 x i8> %dst
+  ret <vscale x 16 x i8> %sel
+}
+
+define <vscale x 8 x i16> @sel_nxv8i16(<vscale x 8 x i1> %p,
+                                       <vscale x 8 x i16> %dst,
+                                       <vscale x 8 x i16> %a) {
+; CHECK-LABEL: sel_nxv8i16:
+; CHECK:         mov z0.h, p0/m, z1.h
+; CHECK-NEXT:    ret
+  %sel = select <vscale x 8 x i1> %p, <vscale x 8 x i16> %a, <vscale x 8 x i16> %dst
+  ret <vscale x 8 x i16> %sel
+}
+
+define <vscale x 4 x i32> @sel_nxv4i32(<vscale x 4 x i1> %p,
+                                       <vscale x 4 x i32> %dst,
+                                       <vscale x 4 x i32> %a) {
+; CHECK-LABEL: sel_nxv4i32:
+; CHECK:         mov z0.s, p0/m, z1.s
+; CHECK-NEXT:    ret
+  %sel = select <vscale x 4 x i1> %p, <vscale x 4 x i32> %a, <vscale x 4 x i32> %dst
+  ret <vscale x 4 x i32> %sel
+}
+
+define <vscale x 2 x i64> @sel_nxv2i64(<vscale x 2 x i1> %p,
+                                       <vscale x 2 x i64> %dst,
+                                       <vscale x 2 x i64> %a) {
+; CHECK-LABEL: sel_nxv2i64:
+; CHECK:         mov z0.d, p0/m, z1.d
+; CHECK-NEXT:    ret
+  %sel = select <vscale x 2 x i1> %p, <vscale x 2 x i64> %a, <vscale x 2 x i64> %dst
+  ret <vscale x 2 x i64> %sel
+}
+
+; Floating point vector select
+
+define <vscale x 8 x half> @sel_nxv8f16(<vscale x 8 x i1> %p,
+                                        <vscale x 8 x half> %dst,
+                                        <vscale x 8 x half> %a) {
+; CHECK-LABEL: sel_nxv8f16:
+; CHECK:         mov z0.h, p0/m, z1.h
+; CHECK-NEXT:    ret
+  %sel = select <vscale x 8 x i1> %p, <vscale x 8 x half> %a, <vscale x 8 x half> %dst
+  ret <vscale x 8 x half> %sel
+}
+
+define <vscale x 4 x float> @sel_nxv4f32(<vscale x 4 x i1> %p,
+                                         <vscale x 4 x float> %dst,
+                                         <vscale x 4 x float> %a) {
+; CHECK-LABEL: sel_nxv4f32:
+; CHECK:         mov z0.s, p0/m, z1.s
+; CHECK-NEXT:    ret
+  %sel = select <vscale x 4 x i1> %p, <vscale x 4 x float> %a, <vscale x 4 x float> %dst
+  ret <vscale x 4 x float> %sel
+}
+
+define <vscale x 2 x float> @sel_nxv2f32(<vscale x 2 x i1> %p,
+                                         <vscale x 2 x float> %dst,
+                                         <vscale x 2 x float> %a) {
+; CHECK-LABEL: sel_nxv2f32:
+; CHECK:         mov z0.d, p0/m, z1.d
+; CHECK-NEXT:    ret
+  %sel = select <vscale x 2 x i1> %p, <vscale x 2 x float> %a, <vscale x 2 x float> %dst
+  ret <vscale x 2 x float> %sel
+}
+
+define <vscale x 2 x double> @sel_nxv8f64(<vscale x 2 x i1> %p,
+                                          <vscale x 2 x double> %dst,
+                                          <vscale x 2 x double> %a) {
+; CHECK-LABEL: sel_nxv8f64:
+; CHECK:         mov z0.d, p0/m, z1.d
+; CHECK-NEXT:    ret
+  %sel = select <vscale x 2 x i1> %p, <vscale x 2 x double> %a, <vscale x 2 x double> %dst
+  ret <vscale x 2 x double> %sel
+}