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authorUlrich Weigand <ulrich.weigand@de.ibm.com>2013-07-01 17:21:23 +0000
committerUlrich Weigand <ulrich.weigand@de.ibm.com>2013-07-01 17:21:23 +0000
commit7a9fcdf6fb84b4d8db49eb0a8488b81155bffb2a (patch)
tree136cc1521cfcb9a5e6b54f8eaa85662cffd56e83
parent98fcc7b6bcbd7f27492003cdb8225fc9c196f63c (diff)
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[PowerPC] Add "wait" instruction
This adds the "wait" instruction and its extended mnemonics. llvm-svn: 185350
-rw-r--r--llvm/lib/Target/PowerPC/PPCInstrInfo.td7
-rw-r--r--llvm/test/MC/PowerPC/ppc64-encoding-bookII.s12
2 files changed, 15 insertions, 4 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index fc925e11e81..5c2c59f21be 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -2260,6 +2260,9 @@ def ICBI : XForm_1a<31, 982, (outs), (ins memrr:$src),
def EIEIO : XForm_24_eieio<31, 854, (outs), (ins),
"eieio", LdStLoad, []>;
+def WAIT : XForm_24_sync<31, 62, (outs), (ins i32imm:$L),
+ "wait $L", LdStLoad, []>;
+
//===----------------------------------------------------------------------===//
// PowerPC Assembler Instruction Aliases
//
@@ -2286,6 +2289,10 @@ def : InstAlias<"sync", (SYNC 0)>;
def : InstAlias<"lwsync", (SYNC 1)>;
def : InstAlias<"ptesync", (SYNC 2)>;
+def : InstAlias<"wait", (WAIT 0)>;
+def : InstAlias<"waitrsv", (WAIT 1)>;
+def : InstAlias<"waitimpl", (WAIT 2)>;
+
def : InstAlias<"xnop", (XORI R0, R0, 0)>;
def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
diff --git a/llvm/test/MC/PowerPC/ppc64-encoding-bookII.s b/llvm/test/MC/PowerPC/ppc64-encoding-bookII.s
index d066003cfb2..b6c2e621d42 100644
--- a/llvm/test/MC/PowerPC/ppc64-encoding-bookII.s
+++ b/llvm/test/MC/PowerPC/ppc64-encoding-bookII.s
@@ -39,7 +39,8 @@
sync 2
# CHECK: eieio # encoding: [0x7c,0x00,0x06,0xac]
eieio
-# FIXME: wait 2
+# CHECK: wait 2 # encoding: [0x7c,0x40,0x00,0x7c]
+ wait 2
# Extended mnemonics
@@ -61,7 +62,10 @@
# CHECK: sync 2 # encoding: [0x7c,0x40,0x04,0xac]
ptesync
-# FIXME: wait
-# FIXME: waitrsv
-# FIXME: waitimpl
+# CHECK: wait 0 # encoding: [0x7c,0x00,0x00,0x7c]
+ wait
+# CHECK: wait 1 # encoding: [0x7c,0x20,0x00,0x7c]
+ waitrsv
+# CHECK: wait 2 # encoding: [0x7c,0x40,0x00,0x7c]
+ waitimpl
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