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author | Tom Stellard <tstellar@redhat.com> | 2019-08-01 05:39:17 +0000 |
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committer | Tom Stellard <tstellar@redhat.com> | 2019-08-01 05:39:17 +0000 |
commit | 7a2958bc20bcd8dd42bef30223da5d0cba08f4d5 (patch) | |
tree | 4db92039a556a354c32d59dc47cc1db86cd2facd | |
parent | 66c320908ba0eea9355c39a945473b5c4d78b805 (diff) | |
download | bcm5719-llvm-7a2958bc20bcd8dd42bef30223da5d0cba08f4d5.tar.gz bcm5719-llvm-7a2958bc20bcd8dd42bef30223da5d0cba08f4d5.zip |
AMDGPU/SILoadStoreOptimizer: Make some functions const
Reviewers: arsenm, pendingchaos, rampitec
Reviewed By: rampitec
Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D65316
llvm-svn: 367517
-rw-r--r-- | llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp index 5a988dd3ae4..b48b66195ec 100644 --- a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp +++ b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp @@ -165,9 +165,9 @@ private: static unsigned getNewOpcode(const CombineInfo &CI); static std::pair<unsigned, unsigned> getSubRegIdxs(const CombineInfo &CI); const TargetRegisterClass *getTargetRegisterClass(const CombineInfo &CI); - unsigned getOpcodeWidth(const MachineInstr &MI); - InstClassEnum getInstClass(unsigned Opc); - unsigned getRegs(unsigned Opc); + unsigned getOpcodeWidth(const MachineInstr &MI) const; + InstClassEnum getInstClass(unsigned Opc) const; + unsigned getRegs(unsigned Opc) const; bool findMatchingInst(CombineInfo &CI); @@ -394,7 +394,7 @@ bool SILoadStoreOptimizer::widthsFit(const GCNSubtarget &STM, } } -unsigned SILoadStoreOptimizer::getOpcodeWidth(const MachineInstr &MI) { +unsigned SILoadStoreOptimizer::getOpcodeWidth(const MachineInstr &MI) const { const unsigned Opc = MI.getOpcode(); if (TII->isMUBUF(MI)) { @@ -413,7 +413,7 @@ unsigned SILoadStoreOptimizer::getOpcodeWidth(const MachineInstr &MI) { } } -InstClassEnum SILoadStoreOptimizer::getInstClass(unsigned Opc) { +InstClassEnum SILoadStoreOptimizer::getInstClass(unsigned Opc) const { if (TII->isMUBUF(Opc)) { const int baseOpcode = AMDGPU::getMUBUFBaseOpcode(Opc); @@ -464,7 +464,7 @@ InstClassEnum SILoadStoreOptimizer::getInstClass(unsigned Opc) { } } -unsigned SILoadStoreOptimizer::getRegs(unsigned Opc) { +unsigned SILoadStoreOptimizer::getRegs(unsigned Opc) const { if (TII->isMUBUF(Opc)) { unsigned result = 0; |