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authorAkira Hatanaka <ahatanak@gmail.com>2011-09-22 17:57:32 +0000
committerAkira Hatanaka <ahatanak@gmail.com>2011-09-22 17:57:32 +0000
commit79a45a839c523beb81b85a1c2554cbc24764acb0 (patch)
treec471bd93a56fdc84bd38848020c29ed992c36516
parenta58fde665ad5c9e0e39b2dcec25cd4ef348b0190 (diff)
downloadbcm5719-llvm-79a45a839c523beb81b85a1c2554cbc24764acb0.tar.gz
bcm5719-llvm-79a45a839c523beb81b85a1c2554cbc24764acb0.zip
Define a new sub-register index sub_32 for accessing the 32-bit sub-register of
a 64-bit integer register. Move the subreg index definitions to the beginning of the file. llvm-svn: 140319
-rw-r--r--llvm/lib/Target/Mips/MipsRegisterInfo.td9
1 files changed, 5 insertions, 4 deletions
diff --git a/llvm/lib/Target/Mips/MipsRegisterInfo.td b/llvm/lib/Target/Mips/MipsRegisterInfo.td
index de0ccbb4fd5..62210210dd9 100644
--- a/llvm/lib/Target/Mips/MipsRegisterInfo.td
+++ b/llvm/lib/Target/Mips/MipsRegisterInfo.td
@@ -10,6 +10,11 @@
//===----------------------------------------------------------------------===//
// Declarations that describe the MIPS register file
//===----------------------------------------------------------------------===//
+let Namespace = "Mips" in {
+def sub_fpeven : SubRegIndex;
+def sub_fpodd : SubRegIndex;
+def sub_32 : SubRegIndex;
+}
// We have banks of 32 registers each.
class MipsReg<string n> : Register<n> {
@@ -34,10 +39,6 @@ class FPR<bits<5> num, string n> : MipsReg<n> {
}
// Mips 64-bit (aliased) FPU Registers
-let Namespace = "Mips" in {
-def sub_fpeven : SubRegIndex;
-def sub_fpodd : SubRegIndex;
-}
class AFPR<bits<5> num, string n, list<Register> subregs>
: MipsRegWithSubRegs<n, subregs> {
let Num = num;
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